XC2C32 XILINX [Xilinx, Inc], XC2C32 Datasheet - Page 7

• Manufacturer Part Number: XC2C32
• Description: CoolRunner-II CPLD Family
• Manufacturer: XILINX [Xilinx, Inc]

Output Banking
CPLDs are widely used as voltage interface translators. To
that end, the output pins are grouped in large banks. The
XC2C32 and XC2C64 devices are not banked, but the new
XC2C32A and XC2C64A devices have two banks. The
medium parts (128 and 256 macrocell) support two output
banks. With two, the outputs will switch to one of two
selected output voltage levels, unless both banks are set to
the same voltage. The larger parts (384 and 512 macrocell)
support four output banks split evenly. They can support
groupings of one, two, three or four separate output voltage
levels. This kind of flexibility permits easy interfacing to
3.3V, 2.5V, 1.8V, and 1.5V in a single part.
DataGATE
Low power is the hallmark of CMOS technology. Other
CPLD families use a sense amplifier approach to creating
product terms, which always has a residual current compo-
nent being drawn. This residual current can be several hun-
dred milliamps, making them unusable in portable systems.
CoolRunner-II CPLDs use standard CMOS methods to cre-
ate the CPLD architecture and deliver the corresponding
low current consumption, without doing any special tricks.
However, sometimes designers would like to reduce their
system current even more by selectively disabling circuitry
not being used.
The patented DataGATE technology was developed to per-
mit a straightforward approach to additional power reduc-
tion. Each I/O pin has a series switch that can block the
arrival of free running signals that are not of interest. Sig-
nals that serve no use may increase power consumption,
and can be disabled. Users are free to do their design, then
choose sections to participate in the DataGATE function.
DataGATE is a logic function that drives an assertion rail
threaded
CoolRunner-II CPLD parts. Designers can select inputs to
be blocked under the control of the DataGATE function,
DS090 (v2.5) June 28, 2005
Product Specification
through
R
the
medium
and
high-density
www.xilinx.com
effectively blocking controlled switching signals so they do
not drive internal chip capacitances. Output signals that do
not switch, are held by the bus hold feature. Any set of input
pins can be chosen to participate in the DataGATE function.
Figure 5
quency graph. With DataGATE, designers can approach
zero power, should they choose to, in their designs
Figure 6
pin drives the DataGATE Assertion Rail. It can have any
desired logic function on it. It can be as simple as mapping
an input pin to the DataGATE function or as complex as a
counter or state machine output driving the DataGATE I/O
pin through a macrocell. When the DataGATE rail is
asserted high, any pass transistor switch attached to it is
blocked. Note that each pin has the ability to attach to the
AIM through a DataGATE pass transistor, and thus be
blocked. A latch automatically captures the state of the pin
when it becomes blocked. The DataGATE Assertion Rail
threads throughout all possible I/Os, so each can participate
if chosen. Note that one macrocell is singled out to drive the
rail, and that macrocell is exposed to the outside world
through a pin, for inspection. If DataGATE is not needed,
this pin is an ordinary I/O.
Figure 5: CMOS I
shows the familiar CMOS I
shows how DataGATE basically works. One I/O
I
CC
0
CC
vs. Switching Frequency Curve
Frequency
CoolRunner-II CPLD Family
CC
DS090_05_101001
versus switching fre-
7