XC2C32 XILINX [Xilinx, Inc], XC2C32 Datasheet - Page 4

• Manufacturer Part Number: XC2C32
• Description: CoolRunner-II CPLD Family
• Manufacturer: XILINX [Xilinx, Inc]

CoolRunner-II CPLD Family
trol path. The BSC and ISP block has the JTAG controller
and In-System Programming Circuits.
Function Block
The CoolRunner-II CPLD Function Blocks contain 16 mac-
rocells, with 40 entry sites for signals to arrive for logic cre-
ation and connection. The internal logic engine is a 56
product term PLA. All Function Blocks, regardless of the
number contained in the device, are identical. For a
high-level view of the Function Block, see
At the high level, it is seen that the product terms (p-terms)
reside in a programmable logic array (PLA). This structure
4
Figure 2: CoolRunner-II CPLD Function Block
I/O Pin
I/O Pin
I/O Pin
JTAG
40
Set/Reset
PLA
BSC and ISP
Global
16
16
MC16
MC1
MC2
Global
Clocks
MC16
MC1
MC2
3
16
Direct Inputs
DS090_02_101001
Figure 1: CoolRunner-II CPLD Architecture
Function
Block 1
PLA
Out
To AIM
Figure
16 FB
2.
40
Clock and Control Signals
www.xilinx.com
BSC Path
AIM
is extremely flexible, and very robust when compared to
fixed or cascaded product term function blocks.
Classic CPLDs typically have a few product terms available
for a high-speed path to a given macrocell. They rely on
capturing unused p-terms from neighboring macrocells to
expand their product term tally, when needed. The result of
this architecture is a variable timing model and the possibil-
ity of stranding unusable logic within the FB.
The PLA is different — and better. First, any product term
can be attached to any OR gate inside the FB macrocell(s).
Second, any logic function can have as many p-terms as
needed attached to it within the FB, to an upper limit of 56.
Third, product terms can be re-used at multiple macrocell
OR functions so that within a FB, a particular logical product
need only be created once, but can be re-used up to 16
times within the FB. Naturally, this plays well with the fitting
software, which identifies product terms that can be shared.
The software places as many of those functions as it can
into FBs, so it happens for free. There is no need to force
macrocell functions to be adjacent or any other restriction
save residing in the same FB, which is handled by the soft-
ware. Functions need not share a common clock, common
set/reset or common output enable to take full advantage of
the PLA. Also, every product term arrives with the same
time delay incurred. There are no cascade time adders for
putting more product terms in the FB. When the FB product
term budget is reached, there is a small interconnect timing
penalty to route signals to another FB to continue creating
logic. Xilinx design software handles all this automatically.
16 FB
40
Function
Block n
PLA
Direct Inputs
MC16
MC1
MC2
16
16
DS090 (v2.5) June 28, 2005
Product Specification
DS090_01_121201
I/O Pin
I/O Pin
I/O Pin
R