XC2C32 XILINX [Xilinx, Inc], XC2C32 Datasheet - Page 3

• Manufacturer Part Number: XC2C32
• Description: CoolRunner-II CPLD Family
• Manufacturer: XILINX [Xilinx, Inc]

Table 4: CoolRunner-II CPLD Family Features
Architecture Description
CoolRunner-II CPLD is a highly uniform family of fast, low
power CPLDs. The underlying architecture is a traditional
CPLD architecture combining macrocells into Function
Blocks (FBs) interconnected with a global routing matrix,
the Xilinx Advanced Interconnect Matrix (AIM). The Func-
tion Blocks use a Programmable Logic Array (PLA) config-
uration which allows all product terms to be routed and
shared among any of the macrocells of the FB. Design soft-
ware can efficiently synthesize and optimize logic that is
subsequently fit to the FBs and connected with the ability to
utilize a very high percentage of device resources. Design
changes are easily and automatically managed by the soft-
ware, which exploits the 100% routability of the Program-
mable Logic Array within each FB. This extremely robust
DS090 (v2.5) June 28, 2005
Product Specification
(1) LVCMOS15 requires the use of Schmitt-trigger inputs.
IEEE 1532
I/O banks
Clock division
DualEDGE Registers
DataGATE
LVTTL
LVCMOS33, 25, 18,
and 15
SSTL2_1
SSTL3_1
HSTL_1
Configurable ground
Quadruple data
security
Open drain outputs
Hot plugging
Schmitt Inputs
(1)
R
XC2C32
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XC2C32A
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XC2C64
www.xilinx.com
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XC2C64A
building block delivers the industry’s highest pinout reten-
tion, under very broad design conditions. The architecture
will be explained by expanding the detail as we discuss the
underlying Function Blocks, logic and interconnect.
The design software automatically manages these device
resources so that users can express their designs using
completely generic constructs without knowledge of these
architectural details. More advanced users can take advan-
tage of these details to more thoroughly understand the
software’s choices and direct its results.
Figure 1
tion Blocks attach to pins and interconnect to each other
within the internal interconnect matrix. Each FB contains 16
macrocells. The BSC path is the JTAG Boundary Scan Con-
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shows the high-level architecture whereby Func-
XC2C128
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XC2C256
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CoolRunner-II CPLD Family
XC2C384
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XC2C512
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