XC2C32 XILINX [Xilinx, Inc], XC2C32 Datasheet - Page 10

• Manufacturer Part Number: XC2C32
• Description: CoolRunner-II CPLD Family
• Manufacturer: XILINX [Xilinx, Inc]

CoolRunner-II CPLD Family
Design Security
Designs can be secured during programming to prevent
either accidental overwriting or pattern theft via readback.
Four independent levels of security are provided on-chip,
eliminating any electrical or visual detection of configuration
patterns. These security bits can be reset only by erasing
the entire device. See
Timing Model
Figure 11
represents one aspect of the overall architecture from a tim-
Table 6: Timing Parameter Definitions
10
Buffer Delays
T
T
T
T
T
T
T
T
P-term Delays
T
T
T
OUT
Symbol
lN
DIN
GCK
GSR
GTS
EN
SLEW
CT
LOGI1
LOGI2
shows the CoolRunner-II CPLD timing model. It
T
T
T
T
T
GCK
GSR
GTS
DIN
IN
Input Buffer Delay
Direct data register input delay
Global clock (GCK) buffer delay
Global set/reset (GSR) buffer delay
Global output enable (GTS) buffer delay
Output buffer delay
Output buffer enable/disable delay
Output buffer slew rate control delay
Control Term delay (single PT or FB-CT)
Single P-term logic delay
Multiple P-term logic delay adder
WP170
T
T
T
T
T
HYS
HYS
HYS
HYS
HYS
for more detail.
Parameter
Figure 11: CoolRunner-II CPLD Timing Model
T
T
CT
LOGI1
T
LOGI2
www.xilinx.com
ing viewpoint. Each little block is a time delay that a signal
will incur if the signal passes through such a resource. Tim-
ing reports are created by tallying the incremental signal
delays as signals progress within the CPLD. Software cre-
ates the timing reports after a design has been mapped
onto the specific part, and knows the specific delay values
for a given speed grade. Equations for the higher level tim-
ing values (i.e., T
summarizes the individual parameters and provides a brief
definition of their associated functions. Xilinx application
note XAPP375 details the CoolRunner-II CPLD family tim-
ing with several examples.
Table 6: Timing Parameter Definitions (Continued)
D/T
CE
Macrocell Delays
T
T
T
T
T
T
T
T
Feedback Delays
T
T
S/R
AOI
Symbol
PDI
SUI
HI
ECSU
ECHO
COI
HYS
F
OEM
T
SUI
T
T
PDI
T
T
T
F
ECHO
AOI
ECSU
T
T
COI
HI
Macro cell input to output valid
Macro register setup before clock
Macro register hold after clock
Macro register enable clock setup time
Macro register enable clock hold time
Macro register clock to output valid
Macro register set/reset to output valid
Hysteresis selection delay adder
Feedback delay
Macrocell to Global OE delay
PD
and F
T
OUT
T
SYSTEM
OEM
Parameter
DS090 (v2.5) June 28, 2005
) are available.
T
EN
Product Specification
XAPP375_03_010303
T
SLEW
Table 6
R