TTSV02622V2-DB AGERE [Agere Systems], TTSV02622V2-DB Datasheet - Page 23

• Manufacturer Part Number: TTSV02622V2-DB
• Description: STS-24 Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

June 2003
Agere Systems Inc.
Transmit Direction (Line to Backplane)
Transport Overhead Serial Link
The TOH serial links are used to insert TOH bytes into the transmit data. TOH_IN and TOH_CLK_EN get retimed
by TOH_CLK in order to meet setup and hold specifications of the device.
Insertion or passthrough of the TOH is under software control.
TOH parity is calculated using the initial retimed data (TOH_IN_D).
A1/A2 Frame Insert and Corruption
When not corrupted, for each stream, all twelve A1 bytes of the STS-12 are set to 0xF6 and all twelve A2 bytes of
the STS-12 are set to 0×28.
Corruption is controlled per stream by the A1/A2 error insert register. When A1/A2 corruption is set for a particular
stream, the A1/A2 value in the corrupted A1/A2 value registers are sent for the number of frames defined in the
corrupted A1/A2 frame count register (see Table 6 on page 33 and Table 7 on page 36 for register details).
Note: When the corrupted A1/A2 frame count register is set to zero, A1A2 corruption will continue until the A1/A2
On a per-device basis, the A1 and A2 byte values are set, as well as the number of frames of corruption. Then, to
insert the specified A1/A2 values, each channel has an enable register. When the enable register is set, the A1/A2
values are corrupted for the number specified in the number of frames to corrupt. To insert errors again, the per-
channel fault insert register must be cleared, and set again.
Only the last A1 and the first A2 are corrupted.
B1 Calculation and Insertion
The B1 calculation block computes a BIP-8 code, using even parity over all bits of the previous STS-n frame after
scrambling and is inserted in the B1 byte of the current STS-n frame before scrambling. Per-bit B1 corruption is
controlled by the force BIP-8 corruption register (per device register). For any bit set in this register, the corre-
sponding bit in the calculated BIP-8 is inverted before insertion into the B1 byte position. Each stream has an inde-
pendent fault insert register that enables the inversion of the B1 bytes. B1 bytes in all other STS-1s in the stream
are passed through transparently.
Stream Disable
When disabled via the appropriate bit in the stream enable register, the prescrambled data for a stream is set to all
ones, feeding the HSI. The HSI macro is powered down on a per-stream basis, as is the LVDS outputs.
Scrambler
The data stream is scrambled using a frame synchronous scrambler of sequence length 127, operating at the line
rate. The scrambling function can be disabled by software.
The generating polynomial for the scrambler is 1 + x
The scrambler is reset to 111_1111 on the first byte of the SPE (byte following the Z0 byte in the twelfth STS-1).
That byte and all subsequent bytes to be scrambled are exclusive ORed, with the output from the byte-wise scram-
bler. The scrambler runs continuously from that byte on throughout the remainder of the frame.
A1, A2, J0, and Z0 bytes are not scrambled.
error insert register is cleared, i.e., indefinitely.
6
+ x
(continued)
7
.
TTSV02622 STS-24 Backplane Transceiver
23