TTSV02622V2-DB AGERE [Agere Systems], TTSV02622V2-DB Datasheet - Page 27

• Manufacturer Part Number: TTSV02622V2-DB
• Description: STS-24 Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

June 2003
Agere Systems Inc.
Receiver Block
B1 Calculate and Descramble (Backplane to Line)
Each Rx block receives byte-wide scrambled 77.76 MHz data and a frame sync from the framer. Since each HSI is
independently clocked, the Rx block operates on individual streams. Timing signals required to locate overhead
bytes to be extracted are generated internally based on the frame sync. The frame sync occurs one clock pulse
before the first A1 byte of the stream. The Rx block produces byte-wide descrambled data and an output frame
sync for the alignment FIFO block. The output frame sync occurs two clocks before the first A1 byte of the
descrambled data stream to allow for metastable hardening by the write control subblock.
On the received data, the following functionality is needed:
Descrambling
The streams are scrambled using a frame synchronous scrambler of sequence length 127, operating at the line
rate. The descrambling function can be disabled by software.
The generating polynomial for the scramble is 1 + x
The scrambler is reset to 1111111 on the first byte of the SPE (byte following the Z0 byte in the twelfth STS-1). That
byte and all subsequent bytes to be scrambled are exclusive ORed, with the output from the byte-wise scrambler.
The scrambler runs continuously from that byte on throughout the remainder of the frame.
A1, A2, J0, and Z0 bytes are not scrambled.
B1 Verification
The B1 calculation block computes a BIP-8 code, using even parity over all bits of the previous STS-12 frame
before descrambling, and this value is checked against the B1 byte of the current frame after descrambling. A per-
stream B1 error counter is incremented for each bit that is in error.
Alarm Indication Signal Line (AIS-L) Insertion
If enabled via AIS_L_INSERT[x] bit in the AIS_L force register, AIS-L is inserted into the received frame by writing
all ones for all bytes of the descrambled stream.
AIS-L Insertion on Out of Frame
If enabled via the appropriate bit in the AIS_L force on out of frame register, AIS-L is inserted into the received
frame by writing all ones for all bytes of the descrambled stream when the framer indicates that an out of frame
condition exists.
Internal Parity Generation
An even parity is generated on all data bytes and is routed in parallel with the data to be checked before the protec-
tion switch MUX at the parallel output.
Descrambling of received data stream with optional descrambling disable.
B1 verification.
(continued)
6
+ x
7
.
TTSV02622 STS-24 Backplane Transceiver
27