TTSV02622V2-DB AGERE [Agere Systems], TTSV02622V2-DB Datasheet - Page 61

• Manufacturer Part Number: TTSV02622V2-DB
• Description: STS-24 Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

June 2003
Agere Systems Inc.
Timing Characteristics
CPU Interface Timing
Table 26. Write Transaction Timing Requirements
INTERNAL REGISTER
T
RD_WR_N
(SYS_CLK
T
T
DOMAIN)
T
T
T
ACCESS_MIN
RD_WR_MAX
T
WRITE_MAX
T
ADDR_MAX
DAT_MAX,
DB_HOLD
Symbol
T
DAT_MAX
INT_MAX
PULSE
RD_WR_N
ADDR[6:0]
,
ADDR_MAX
DB[7:0]
INT_N
CS_N
T
T
RD_WR_MAX
ADDR_MAX
,
Minimum Pulse Width for CS_N
Maximum Time from Negative Edge of CS_N to ADDR Valid
Maximum Time from Negative Edge of CS_N to Data Valid
Maximum Time from Negative Edge of CS_N to Negative
Maximum Time from Negative Edge of CS_N to Contents of
Minimum Time Between a Write Cycle (falling edge of
Maximum Time from Register FF to Pad
Minimum Hold Time that RD_WR_N, ADDR, and DB Must
(continued)
Edge of RD_WR_N
Internal Register Latching DB[7:0]
CS_N) and Any other Transaction (read or write, at falling
edge of CS_N)
Be Held Valid from the Negative Edge of CS_N
T
RD_WR_N, ADDR_MAX, DB_HOLD
T
Figure 20. Write Transaction
WRITE_MAX
OLD VALUE
DATA VALID
T
ACCESS_MIN
Parameter
TTSV02622 STS-24 Backplane Transceiver
NEW VALUE
T
INT_MAX
T
PULSE
Min
60
57
—
—
—
—
—
5
Max
18
25
26
60
20
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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