TTSV02622V2-DB AGERE [Agere Systems], TTSV02622V2-DB Datasheet - Page 58
TTSV02622V2-DB
Manufacturer Part Number
TTSV02622V2-DB
Description
STS-24 Backplane Transceiver
Manufacturer
AGERE [Agere Systems]
Datasheet
1.TTSV02622V2-DB.pdf
(64 pages)
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TTSV02622 STS-24 Backplane Transceiver
Timing Characteristics
Table 23. Protection Switch Timing Requirements
Notes:
Output bus refers to 8 bits data, 1 bit parity, 1 bit SPE, and 1 bit C1J1.
Channel A refers to whether the PROT_SW_A pins that are activated. For example, if the PROT_SW_A pin is activated, the timing diagram for
Min/max variation on T
58
Symbol
output bus A refers to output bus A.
T
T
T
T
T
HIZ
CH
SU
HD
TR
Transport Delay from Latching of PROT_SW_A to Actual Data
Transport Delay from Latching of PROT_SW_A to Actual Data
Propagation Delay from SYS_CLK to HI_Z of Output Bus
Setup Time Required from Change in PROT_SW_A to Rising
Hold Time Required from Rising SYS_CLK to Change in
Switch
HI-Z
SYS_CLK
PROT_SW_A
OUTPUT BUS*
OUTPUT BUS
PROT_SW_A
RT
A & B
SYS_CLK
SYS_CLK
and T
A
HIZ
due to clock phase selected in clock recovery block.
(continued)
CH A & B
T
CH A
Parameter
HD
Figure 17. Protection Switch Timing
CH A & B
CH A
T
SU
CH A & B
CH A
CH A & B
CH A
T
T
HIZ
TR
Min
—
—
—
3
0
Typ
—
—
—
8
5
CH B
Max
T
25
—
—
—
—
CH
Agere Systems Inc.
Leading edge
Leading edge
SYS_CLKs
SYS_CLKs
June 2003
Unit
ns
ns
ns
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