TTSV02622V2-DB AGERE [Agere Systems], TTSV02622V2-DB Datasheet - Page 36

• Manufacturer Part Number: TTSV02622V2-DB
• Description: STS-24 Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

TTSV02622 STS-24 Backplane Transceiver
Register Descriptions
Table 7. Register Description
36
Address
(hex)
00
01
02
03
04
05
06
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:2]
Bit
0
1
FIFO ALIGNMENT
GLOBAL RESET
LOCKREG MSB
SCRATCH PAD
LOCKREG LSB
FIXED ID MSB
FIXED ID LSB
FIXED REV
COMMAND
COMMAND
Name
CREG The scratch pad has no function and is not used any-
SREG NA.
SREG NA.
SREG NA.
CREG In order to write to registers in memory locations 06—7F,
CREG See address 0x04 bits [7:0] description.
PREG The FIFO ALIGNMENT and GLOBAL RESET COM-
PREG See address 0x06 bit 0 description.
Type
where in the TTSV02622 chip. However, this register can
be written to and read from.
LOCKREG MSB and LOCKREG LSB must be respec-
tively set to the values of A0 and 01. If the LOCKREG
MSB and LOCKREG LSB values are not set to A0 and 01
respectively, then any values written to the registers in
memory locations 06—7F will be ignored.
After reset (both hard and soft), the TTSV02622 chip is in
a write locked mode. The TTSV02622 chip needs to be
unlocked before it can be written to.
Also note that the scratch pad register (03) can always be
written to since it is unaffected by write lock mode.
MANDS are both accessed via the pulse register in mem-
ory address 06. The FIFO ALIGNMENT command is
used to frame align the outputs of the four receive STM
stream FIFOs. The GLOBAL RESET COMMAND is a soft
(software initiated) reset. Nevertheless, the GLOBAL
RESET COMMAND will have the exact reset effect as a
hard (RST_N pin) reset.
Reserved.
Description
Agere Systems Inc.
June 2003
Reset
Value
(hex)
NA
A0
01
01
00
00
00