TTSV02622V2-DB AGERE [Agere Systems], TTSV02622V2-DB Datasheet - Page 24

• Manufacturer Part Number: TTSV02622V2-DB
• Description: STS-24 Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

TTSV02622 STS-24 Backplane Transceiver
Receiver Block
Framer Subblock (Backplane to Line)
The framer block takes byte-wide data from the HSI, and outputs a byte-aligned byte-wide stream and 8 kHz sync
pulse (asserted one clock before the first A1 byte). The framer algorithm determines the out-of-frame/in-frame sta-
tus of the incoming data and will cause interrupts on both an errored frame and an OOF state.
Features
24
(SOFT CTL)
FUNCTION
SWITCH
SWITCH
FRAME
PROT
A1—A2 framing pattern detection.
Framing similar to SONET specification.
Generates timing and an 8 kHz frame pulse.
Detects OOF and generates an interrupt.
Detects errored frame and increments counter.
PROT
LINE
PARITY(1)
OUT BUS
(SOFT CTL)
DATA(8)
C1J1(1)
SPE(1)
SWITCH
CH#1
(77.76 MHz)
PROT
ENA
SYSTEM
(SOFT CTL)
CLOCK
(FROM TX)
SWITCH
HI-Z
SYSTEM
PROT
CTL
FRAME
(SOFT CTL)
CH#1—2
MUX
(SOFT CTL)
LINE LPBK
OUT DATA
(TO TX)
LPBK
LINE
CH#2
(SOFT CTL)
EVEN/ODD
(TO/FROM
PARITY
OTHER
CTLS
CH)
/CHECK
PARTIY
(SOFT CTL)
GEN
BUS
(SOFT CTL)
PAR ERR
INSERT
/REGEN
K1/K2
PASS
(SOFT REG)
PAR ERR
FLAG
DATA
PARTIY
SPE
C1J1
POINTER
(SOFT REG)
MOVER
MONITORS
STS-12
PERF
(SOFT CTL)
(SOFT CTL)
PAR ERR
CH#1—2 MUX
ON LOF
INSERT
(SOFT CTL)
AIS-L
(SOFT CTL)
OUT DATA
FORCE
AIS-L
Figure 8. Receiver Block
FP
CONVERTER
(TO OTHER
CH#2
PAR TO SER
(SOFT
+ BUFFER
INS
CTL)
AIS
HI-Z
CTLS
CH)
TOH SERIAL
TOH
DATA OUT
LOF
FIFO READ/WRITE
FP
1
RD
(SOFT CTL)
RE-ALIGN
(COMMON TO
CHANNELS)
CONTROL
FIFO SYNC
FIFO
0
(COMMON TO
ALIGNER
TOH CLOCK
THE 2
THE 2 CH)
FIFO
CTLS
ALARM FLAG
(SOFT REG)
OFFSET
FRAME
(COMMON TO
(COMMON TO
WR
TOH CLOCK
TOH PORT
CONTROL
THE 2 CH)
THE 2 CH)
ENABLE
FP
FP
(TO OTHER
PAR
GEN
(COMMON TO
CTLS
TOH FRAME
CH)
THE 2 CH)
FP
B1
HI-Z
(SOFT
CTL)
THRESHOLDS
DESCRAM-
(SOFT REG)
PAR ERR FLAG
SONET
MIN/MAX
B1 PAR ERR
(SOFT REG)
PARITY
ERROR
COUNT
BLER
COUNT, B1
FIFO
B1
ALARM FLAG
THRESHOLD
(SOFT REG)
FP
A1/A2 ERR COUNT
FIFO
LOF COUNT,
RECOVERY
LOF FLAG,
(SOF REG)
FRAME
SONET
DESCRAMBLER
(SOFT CTL)
DISABLE
16—622 MHz
(FROM PLL)
(MEGACELL
FROM ASIC
Agere Systems Inc.
PARALLEL
FP = FRAME PULSE
VENDOR)
CLOCKS
SERIAL
TO
77.76 MHz
RX CLK
LVDS LPBK
(SOFT CTL)
June 2003
LPBK
LVDS LPBK
MUX
(FROM TX)
LVDS
#1