TTSV02622V2-DB AGERE [Agere Systems], TTSV02622V2-DB Datasheet - Page 60

• Manufacturer Part Number: TTSV02622V2-DB
• Description: STS-24 Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

TTSV02622 STS-24 Backplane Transceiver
Timing Characteristics
Table 25. Output Serial Port Timing Requirements
Note: The total delay from A1 STS-1 #1 arriving at LVDS input to RX_TOH_FP is 56 SYS_CLKs, and 6 TOH_CLKs. This will vary by
60
T
T
SERIAL 622 Mbits/s
TRANS_SYS
TRANS_TOH
Symbol
±14 SYS_CLKs, 12 each way for the FIFO alignment, and ± 2 SYS_CLKs due to the variability in the clock recovery of the CDR macro.
INPUT LVDS
T
TOH SERIAL
DATA
CO
RX TOH FP
OUTPUT
TOH_CLK
CLK ENA
RX TOH
Data Clock to Out
Delay from First A1 LVDS Serial Input to Transfer to
Delay from Transfer to TOH_CLK to RX_TOH_FP
TOH_CLK
36 bytes TOH
OF A1 BYTE
MSBIT(7)
STS-1 #1
T
TRANS_TOH
(continued)
T
ROW #1
CO
T
TRANS_SYS
Figure 19. Output Serial Port Timing
OF A1 BYTE
1044 bytes SPE
STS-1 #1
STS-1 #1
BIT 6
Parameter
OF A1 BYTE
STS-1 #1
BIT 0
ROW #9
1044 bytes SPE
Min
44
—
2
Typ
56
—
6
Max
Agere Systems Inc.
68
—
8
36 bytes TOH
TOH_CLKs
SYS_CLKs
June 2003
Unit
ns