CY7C68034-56LTXI Cypress Semiconductor, CY7C68034-56LTXI Datasheet

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... Uses external clock or asynchronous strobes ❐ Easy interface to ASIC and DSP ICs ■ Available in space saving 56-pin QFN package CY7C68034 Only Silicon Features ■ Ideal for battery powered applications Suspend current: 100 A (typ) ❐ CY7C68033 Only Silicon Features ■ ...

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... Industry standard ECC NAND Flash correction ❐ 1 bit for every 256-bit correction ❐ 2-bit error detection Document Number: 001-04247 Rev. *J CY7C68033/CY7C68034 ■ Industry standard (SmartMedia) page management for wear leveling algorithm, bad block handling, and physical to logical management. ■ 8-bit NAND Flash interface support ■ ...

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... ECC Generation ........................................................ 13 Autopointer Access ................................................... 14 I2C Controller ............................................................ 14 Pin Assignments ............................................................ 15 Register Summary .......................................................... 21 Absolute Maximum Ratings .......................................... 28 Operating Conditions ..................................................... 28 Document Number: 001-04247 Rev. *J CY7C68033/CY7C68034 DC Characteristics ......................................................... 28 USB Transceiver ....................................................... 28 AC Electrical Characteristics ........................................ 28 USB Transceiver ....................................................... 28 Slave FIFO Asynchronous Read ............................... 29 Slave FIFO Asynchronous Write ............................... 29 Slave FIFO Asynchronous Packet End Strobe ......... 30 Slave FIFO Output Enable ...

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... Overview Cypress Semiconductor Corporation’s EZ-USB (CY7C68033/CY7C68034 firmware-based, programmable version of the EZ-USB NX2LP (CY7C68023/CY7C68024), which is a fixed-function, low power USB 2.0 NAND Flash controller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a program- mable peripheral interface in a single chip, Cypress has created a very cost-effective solution that enables feature-rich NAND Flash-based applications ...

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... PLL 12-pF capacitor values assumes a trace capacitance per side on a four-layer FR4 PCA Document Number: 001-04247 Rev. *J CY7C68033/CY7C68034 Special Function Registers Certain 8051 SFR addresses are populated to provide fast access to critical NX2LP-Flex functions. These SFR additions are shown in Table 1 on page non-standard, enhanced 8051 registers. The two SFR rows that end with ‘ ...

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... IOC IOD INT2CLR IOE INT4CLR OEA OEB OEC OED OEE IE IP EP2468STAT EP01STAT EP24FIFOFLGS GPIFTRIG EP68FIFOFLGS GPIFSGLDATH GPIFSGLDATLX AUTOPTRSETUP GPIFSGLDATLNOX and Manufacturing Mode on page CY7C68033/CY7C68034 SCON1 PSW ACC B SBUF1 T2CON EICON EIE EIP RCAP2L RCAP2H TL2 TH2 7. Page ...

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... EZ-USB microcontrollers. This is due to the additional NAND boot logic that is present in the NX2LP-Flex ROM space. Also, these values are fixed and cannot be changed in the firmware. CY7C68033/CY7C68034 Default VID/PID/DID 0x04B4 Cypress Semiconductor ® ...

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... Bus errors exceeded the programmed limit Reserved Reserved Reserved EP2ISOERR ISO EP2 OUT PID sequence error EP4ISOERR ISO EP4 OUT PID sequence error EP6ISOERR ISO EP6 OUT PID sequence error EP8ISOERR ISO EP8 OUT PID sequence error CY7C68033/CY7C68034 Notes Table 4 on page 9 shows the Page ...

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... This pin has hysteresis and is active LOW. When a crystal is RESET RESET Power-on Reset Note 1. If the external clock is powered at the same time as the CY7C68033/CY7C68034 and has a stabilization wait period, it must be added to the 200 s. Document Number: 001-04247 Rev. *J Source EP2PF Endpoint 2 programmable flag EP4PF Endpoint 4 programmable flag EP6PF ...

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... E780 E77F E740 E73F E700 E6FF E500 E4FF E480 E47F E400 E3FF E200 E1FF E000 CY7C68033/CY7C68034 FFFF 7.5 kBytes USB registers and 4 kBytes FIFO buffers (RD#, WR#) E200 E1FF 512 Bytes RAM Data (RD#, WR#)* E000 3FFF 15 kBytes RAM Code and Data (PSEN#, RD#, ...

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... EP8 EP8 512 512 512 512 1024 1024 512 512 512 512 CY7C68033/CY7C68034 8 EP2 EP2 EP2 EP2 512 1024 1024 512 1024 512 EP6 1024 ...

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... CY7C68033/CY7C68034 int 64 int 64 int 64 int 64 int out (2×) 64 iso out (2×) 64 bulk out (2×) 64 bulk out (2×) 64 int in (2× ...

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... The NAND boot logic uses the Note 5. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation. Document Number: 001-04247 Rev. *J CY7C68033/CY7C68034 same configuration to implement 100-ns timing on the NAND bus to support proper detection of all NAND Flash types. GPIF The GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable finite state machine ...

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... After the ECC is calculated, the value in ECC1 does not change until ECCRESET is written again, even if more data is subsequently passed across the interface Document Number: 001-04247 Rev. *J CY7C68033/CY7C68034 Autopointer Access NX2LP-Flex provides two identical autopointers. They are similar to the internal 8051 data pointers, but with an additional feature: they can optionally increment after every memory access ...

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... PA0/INT0#   GPIO8 GPIO8  GPIO8  GPIO9 GPIO9 GPIO9 CY7C68033/CY7C68034 details the pinout of the 56-pin package Default NAND Firmware Use  CE7#/GPIO7  CE6#/GPIO6  CE5#/GPIO5  CE4#/GPIO4  ...

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... Figure 10. CY7C68033/CY7C68034 56-pin QFN Pin Assignment RDY0/*SLRD 1 RDY1/*SLWR 2 AVCC 3 XTALOUT 4 XTALIN 5 AGND 6 AVCC 7 DPLUS 8 DMINUS 9 AGND 10 VCC 11 GND 12 GPIO8 13 RESERVED# 14 Document Number: 001-04247 Rev. *J CY7C68033/CY7C68034 RESET# 42 GND 41 PA7/*FLAGD/SLCS# 40 PA6/*PKTEND 39 PA5/FIFOADR1 38 PA4/FIFOADR0 37 PA3/*WU2 36 PA2/*SLOE 35 PA1/INT1# 34 PA0/INT0# ...

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... Multiplexed pin whose function is selected by IFCONFIG[1:0]. CTL2 is a GPIF control output. FLAGC is a programmable slave-FIFO output status flag signal. Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins. RE1 NAND read enable output signal. CY7C68033/CY7C68034 Description Reset and for more details. Page ...

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... WP_NF# is the NAND write-protect control output signal. I/O/Z I (PA5) Multiplexed pin whose function is selected by IFCONFIG[1:0]. PA5 is a bidirectional I/O port pin. FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7:0] or FD[15:0]. WP_SW# is the NAND write-protect switch input signal. CY7C68033/CY7C68034 Description Page ...

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... FD[7] is the bidirectional FIFO/GPIF data bus. DD7 is a bidirectional NAND data bus signal. I/O/Z I (PD0) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus. CE0 NAND chip enable output signal. CY7C68033/CY7C68034 Description polarity is programmable via Page ...

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... GPIO7 is a general purpose I/O signal. Power N/A Analog V . Connect this pin to 3.3 V power source. This signal CC provides power to the analog section of the chip. Ground N/A Analog Ground. Connect to ground with as short a path as possible. Power N Connect to 3.3 V power source. CC Ground N/A Ground. CY7C68033/CY7C68034 Description Page ...

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... PL4 PL3 PL7 PL6 PL5 PL4 PL3 PL7 PL6 PL5 PL4 PL3 CY7C68033/CY7C68034 Default xxxxxxxx reserved reserved reserved 00000000 CLKINV CLKOE 8051RES 00000010 GSTATE IFCFG1 IFCFG0 10000000 FLAGA2 FLAGA1 FLAGA0 00000000 FLAGC2 ...

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... EDGEPF EP8 EP6 EP4 0 0 EP8 EP6 EP4 EP8 EP6 EP4 EP2 EP1 CY7C68033/CY7C68034 Default 00000000 LINE10 LINE9 LINE8 00000000 LINE2 LINE1 LINE0 00000000 COL0 LINE17 LINE16 00000000 LINE10 LINE9 LINE8 00000000 LINE2 ...

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... BC3 BC6 BC5 BC4 BC3 BC6 BC5 BC4 BC3 BC6 BC5 BC4 BC3 CY7C68033/CY7C68034 Default EP0 0 IBN xxxxxx0x SUTOK SOF SUDAV 00000000 SUTOK SOF SUDAV 0xxxxxxx EP1IN EP0OUT EP0IN 00000000 EP1IN EP0OUT EP0IN ...

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... CTL3 TRICTL 0 CTL5 CTL4 CTL3 GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 FSE LFUNC1 LFUNC0 TERMA2 TERMA1 TERMA0 CY7C68033/CY7C68034 Default 0 BC9 BC8 000000xx BC2 BC1 BC0 xxxxxxxx 0 BUSY STALL 10000000 0 BUSY STALL 00000000 0 BUSY STALL 00000000 EMPTY ...

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... SAS TCXRDY5 RDY5 RDY4 RDY3 CY7C68033/CY7C68034 Default CTL2 CTL1 CTL0 00000000 CTL2 CTL1 CTL0 00000000 HOCTL2 HOCTL1 HOCTL0 00010010 MSTB2 MSTB1 MSTB0 00100000 0 FALLING RISING 00000001 ...

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... CY7C68033/CY7C68034 Default xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0 0 400 kHz xxxxxxxx xxxxxxxx 00000111 00000000 ...

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... D11 RS1 RS0 1 ERESI RESI INT6 EX6 EX5 PX6 PX5 CY7C68033/CY7C68034 Default PX1 PT0 PX0 10000000 EP1INBSY EP1OUTBS EP0BSY 00000000 Y RW EP1 EP0 10000xxx D10 D9 D8 xxxxxxxx xxxxxxxx ...

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... V < OUT I = –4 mA OUT Except D+/D– D+/D– Connected Disconnected Connected Disconnected 8051 running, connected to USB HS 8051 running, connected to USB FS Before bMaxPower granted by host V min = 3 CY7C68033/CY7C68034 Min Typ Max Unit 3.00 3.3 3.60 V s 200 – – 2 – 5.25 V –0.5 – 0 – ...

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... MHz IFCLK. x Document Number: 001-04247 Rev RDpwh t RDpwl t XFLG t XFD N N OEon OEoff [20] Description t WRpwh t WRpwl t t FDH SFD t XFD Description CY7C68033/CY7C68034 [19] Min Max Unit 50 – – ns – – – 10.5 ns – 10.5 ns [19] [21] Min Max Unit 50 – ...

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... Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. 24. Dashed lines denote signals with programmable polarity. Document Number: 001-04247 Rev PEpwl FLAGS t XFLG [23] Description t t OEon Description CY7C68033/CY7C68034 [22] t PEpwh Min 50 50 – [24] OEoff Min – – Max Unit – ...

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... Notes 25. Dashed lines denote signals with programmable polarity. 26. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document Number: 001-04247 Rev XFLG t XFD N N+1 Description t FAH t SFA [26] Description CY7C68033/CY7C68034 [25] Min Max Unit – 10.7 ns – 14.3 ns [25] Min Max Unit 10 – ...

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... Note In burst read mode, during SLOE is assertion, the data bus driven state and outputs the previous data. After SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incremented. CY7C68033/CY7C68034 [27] t FAH t ...

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... SLWR and the PKTEND signal before the SFD at the same time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum de-asserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion. CY7C68033/CY7C68034 [28] t FAH t WRpwl WRpwh ...

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... Ordering Information Ordering Code Silicon for battery-powered applications CY7C68034-56LTXC CY7C68034-56LTXI Silicon for non-battery-powered applications CY7C68033-56LTXC Development Kit CY3686 Ordering Code Definitions 03X - 56 LT Document Number: 001-04247 Rev × 8 mm, 56-pin QFN (Sawn) 8 × 8 mm, 56-pin QFN (Sawn) 8 × 8 mm, 56-pin QFN (Sawn) ...

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... Package Diagrams Figure 20. 56-pin QFN (8 × 8 × 1.0 mm) LT56B 4.5 × 5.2 EPAD (Sawn), 001-53450 Document Number: 001-04247 Rev. *J CY7C68033/CY7C68034 001-53450 *B Page ...

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... Amkor’s Eutectic and Lead-Free CSP Scale Packages. This application note provides detailed information on board mounting guidelines, soldering flow, rework process, and so on. and High Speed USB Platform Design CY7C68033/CY7C68034 Application Note for Surface Mount Assembly of nl ™ Wafer Level Chip Guidelines. Page ...

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... Cu Fill Cu Fill 0.013” dia This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane. Figure 22. Plot of the Solder Mask (White Area) Figure 23. X-ray Image of the Assembly CY7C68033/CY7C68034 PCB Material Page ...

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... ROM read only memory SCL serial clock SDA serial data line SIE serial interface engine USB universal serial bus Document Number: 001-04247 Rev. *J CY7C68033/CY7C68034 Document Conventions Units of Measure Symbol Unit of Measure °C degree Celsius kHz kilohertz MHz megahertz µA microampere µ ...

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... Sales, Solutions and Legal Information. SHAH / Added Contents and Acronyms AESA Updated Default NAND Firmware Features Formatted table footnotes. ODC Updated Package Diagrams Added Units of Measure. Updated in new template. GAYA Updated Ordering Information CY7C68033/CY7C68034 (Removed Package Drawing 51-85144). with part number CY7C68034-56LTXI. Page ...

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... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-04247 Rev. *J All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB Revised July 6, 2012 CY7C68033/CY7C68034 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 ...