CY7C68034-56LTXI Cypress Semiconductor, CY7C68034-56LTXI Datasheet - Page 13

• Manufacturer Part Number: CY7C68034-56LTXI
• Description: USB Interface IC EZ-USB NX2LP-Flex Flash Controller
• Manufacturer: Cypress Semiconductor

Specifications of CY7C68034-56LTXI

• Rohs: yes
• Product: USB 2.0
• Data Rate: 96 Mbps
• Interface Type: I2C
• Operating Supply Voltage: 3.3 V
• Operating Supply Current: 43 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-56
• Minimum Operating Temperature: - 40 C

External FIFO Interface
Architecture
The NX2LP-Flex slave FIFO architecture has eight 512-byte
blocks in the endpoint RAM that directly serve as FIFO
memories, and are controlled by FIFO control signals (such as
SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).
In operation, some of the eight RAM blocks fill or empty from the
SIE, while the others are connected to the I/O transfer logic. The
transfer logic takes two forms: the GPIF for internally generated
control signals or the slave FIFO interface for externally
controlled transfers.
Master/Slave Control Signals
The NX2LP-Flex endpoint FIFOS are implemented as eight
physically distinct 256 × 16 RAM blocks. The 8051/SIE can
switch any of the RAM blocks between two domains, the USB
(SIE) domain and the 8051-I/O Unit domain. This switching is
done virtually instantaneously, giving essentially zero transfer
time between ‘USB FIFOS’ and ‘Slave FIFOS’. Since they are
physically the same memory, no bytes are actually transferred
between buffers.
At any time, some RAM blocks are filling/emptying with USB data
under SIE control, while other RAM blocks are available to the
8051 and/or the I/O control unit. The RAM blocks operate as
single-port in the USB domain and dual-port in the 8051-I/O
domain. The blocks can be configured as single, double, triple,
or quad buffered as previously shown.
The I/O control unit implements either an internal-master (M for
master) or external-master (S for Slave) interface.
In master (M) mode, the GPIF internally controls FIFOADR[1:0]
to select a FIFO. The two RDY pins can be used as flag inputs
from an external FIFO or other logic if desired. The GPIF can be
run from an internally derived clock (IFCLK), at a rate that
transfers data up to 96 Megabytes/s (48 MHz IFCLK with 16-bit
interface).
In slave (S) mode, the NX2LP-Flex accepts an internally derived
clock (IFCLK, max. frequency 48 MHz) and SLCS#, SLRD,
SLWR, SLOE, PKTEND signals from external logic. Each
endpoint can individually be selected for byte or word operation
by an internal configuration bit and a Slave FIFO output enable
signal SLOE enables data of the selected width. External logic
must ensure that the output enable signal is inactive when writing
data to a slave FIFO. The slave interface must operate
asynchronously, where the SLRD and SLWR signals act directly
as strobes, rather than a clock qualifier as in a synchronous
mode. The signals SLRD, SLWR, SLOE and PKTEND are gated
by the signal SLCS#.
GPIF and FIFO Clock Rates
An 8051 register bit selects one of two frequencies for the
internally supplied interface clock: 30 MHz and 48 MHz. A bit
within the IFCONFIG register inverts the IFCLK signal.
The default NAND firmware image implements a 48 MHz
internally supplied interface clock. The NAND boot logic uses the
Document Number: 001-04247 Rev. *J
Note
5. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
same configuration to implement 100-ns timing on the NAND bus
to support proper detection of all NAND Flash types.
GPIF
The GPIF is a flexible 8- or 16-bit parallel interface driven by a
user-programmable finite state machine. It enables the
NX2LP-Flex to perform local bus mastering and can implement
a wide variety of protocols such as 8-bit NAND interface, printer
parallel port, and Utopia. The default NAND firmware and boot
logic uses GPIF functionality to interface with NAND Flash.
The GPIF on the NX2LP-Flex features three programmable
control outputs (CTL) and two general purpose ready inputs
(RDY). The GPIF data bus width can be 8 or 16 bits. Because
the default NAND firmware image implements an 8-bit data bus
and up to eight chip enable pins on the GPIF ports, it is
recommended that designs based upon the default firmware
image also use an 8-bit data bus.
Each GPIF vector defines the state of the control outputs and
determines what state a ready input (or multiple inputs) must be
before proceeding. The GPIF vector can be programmed to
advance a FIFO to the next data value, advance an address, and
so on. A sequence of the GPIF vectors make up a single
waveform that is executed to perform the desired data move
between the NX2LP-Flex and the external device.
Three Control OUT Signals
The NX2LP-Flex exposes three control signals, CTL[2:0]. CTLx
waveform edges can be programmed to make transitions as fast
as once per clock (20.8 ns using a 48 MHz clock).
Two Ready IN Signals
The 8051 programs the GPIF unit to test the RDY pins for GPIF
branching. The 56-pin package brings out two signals, RDY[1:0].
Long Transfer Mode
In GPIF master mode, the 8051 appropriately sets GPIF
transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1,
or GPIFTCB0) for unattended transfers of up to 2
The GPIF automatically throttles data flow to prevent underflow
or overflow until the full number of requested transactions
complete. The GPIF decrements the value in these registers to
represent the current status of the transaction.
ECC Generation
The NX2LP-Flex can calculate error correcting codes (ECCs) on
data that passes across its GPIF or slave FIFO interfaces. There
are two ECC configurations:
■
■
The following two ECC configurations are selected by the ECCM
bit. The ECC can correct any one-bit error or detect any two-bit
error.
Two ECCs, each calculated over 256 bytes (SmartMedia
Standard)
One ECC calculated over 512 bytes.
[5]
CY7C68033/CY7C68034
32
Page 13 of 40
transactions.