CY7C68034-56LTXI Cypress Semiconductor, CY7C68034-56LTXI Datasheet - Page 10

• Manufacturer Part Number: CY7C68034-56LTXI
• Description: USB Interface IC EZ-USB NX2LP-Flex Flash Controller
• Manufacturer: Cypress Semiconductor

Specifications of CY7C68034-56LTXI

• Rohs: yes
• Product: USB 2.0
• Data Rate: 96 Mbps
• Interface Type: I2C
• Operating Supply Voltage: 3.3 V
• Operating Supply Current: 43 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-56
• Minimum Operating Temperature: - 40 C

Table 5. Reset Timing Values
Wakeup Pins
The 8051 puts itself and the rest of the chip into a power down
mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic, the oscillator
restarts, after the PLL stabilizes, and then the 8051 receives a
wakeup interrupt. This applies whether or not NX2LP-Flex is
connected to the USB.
The NX2LP-Flex exits the power down (USB suspend) state
using one of the following methods:
■
■
■
The second wakeup pin, WU2, can also be configured as a GPIO
pin. This enables a simple external R-C network to be used as a
periodic wakeup source. Note that WAKEUP is, by default, active
LOW.
Program/Data RAM
Internal ROM/RAM Size
The NX2LP-Flex has 1 kBytes ROM and 15 kBytes of internal
program/data RAM, where PSEN#/RD# signals are internally
ORed to enable the 8051 to access it as both program and data
memory. No USB control registers appear in this space.
Internal Code Memory
This mode implements the internal block of RAM (starting at
0x0500) as combined code and data memory, as shown in
Figure
Only the internal and scratch pad RAM spaces have the following
access:
■
■
■
Document Number: 001-04247 Rev. *J
Power-on reset with crystal
Power-on reset with external
clock source
Powered reset
USB bus activity (if D+/D– lines are left floating, noise on these
lines may indicate activity to the NX2LP-Flex and initiate a
wakeup).
External logic asserts the WAKEUP pin
External logic asserts the PA3/WU2 pin.
USB download (only supported by the Cypress manufacturing
tool)
Setup data pointer
NAND boot access.
6.
Condition
200 s + Clock stability time
T
200 s
5 ms
RESET
Figure 6. Internal Code Memory
Register Addresses
Figure 7. Internal Register Addresses
F000
EFFF
FFFF
E800
E7FF
E7C0
E780
E740
E700
E6FF
E4FF
E47F
E400
E1FF
E7BF
E77F
E73F
E500
E480
E3FF
E200
E000
*SUDPTR, USB download, NAND boot access
FFFF
E200
E1FF
E000
3FFF
0500
0000
128 bytes GPIF Waveforms
8051 Addressable Registers
64 Bytes EP0 IN/OUT
64 Bytes RESERVED
2 KBytes RESERVED
512 Bytes RAM Data
Reserved (512)
4 KBytes EP2-EP8
64 Bytes EP1IN
64 Bytes EP1OUT
Reserved (128)
CY7C68033/CY7C68034
8051 xdata RAM
15 kBytes RAM
Code and Data
USB registers
(PSEN#, RD#,
(RD#, WR#)*
and 4 kBytes
512 bytes
FIFO buffers
1 kbyte ROM
(RD#, WR#)
(8 × 512)
7.5 kBytes
buffers
(512)
WR#)*
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