CY7C68034-56LTXI Cypress Semiconductor, CY7C68034-56LTXI Datasheet - Page 18

• Manufacturer Part Number: CY7C68034-56LTXI
• Description: USB Interface IC EZ-USB NX2LP-Flex Flash Controller
• Manufacturer: Cypress Semiconductor

Specifications of CY7C68034-56LTXI

• Rohs: yes
• Product: USB 2.0
• Data Rate: 96 Mbps
• Interface Type: I2C
• Operating Supply Voltage: 3.3 V
• Operating Supply Current: 43 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-56
• Minimum Operating Temperature: - 40 C

Table 8. NX2LP-Flex Pin Descriptions (continued)
Document Number: 001-04247 Rev. *J
QFN Pin
Port A
Number
56-pin
13
14
15
16
44
33
34
35
36
37
38
GPIO8
Reserved#
SCL
SDATA
WAKEUP
PA0 or INT0#
PA1 or INT1#
PA2 or SLOE
PA3 or WU2
PA4 or
FIFOADR0
PA5 or
FIFOADR1
Default Pin
Name
Firmware
WP_SW#
WP_NF#
Unused
Usage
GPIO8
LED1#
LED2#
NAND
CLE
ALE
N/A
N/A
N/A
Type
I/O/Z
Input
Input
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Pin
OD
OD
[6]
Default
I (PA0) Multiplexed pin whose function is selected by PORTACFG[0]
I (PA1) Multiplexed pin whose function is selected by PORTACFG[1]
I (PA2) Multiplexed pin whose function is selected by IFCONFIG[1:0].
I (PA3) Multiplexed pin whose function is selected by WAKEUP[7] and
I (PA4) Multiplexed pin whose function is selected by IFCONFIG[1:0].
I (PA5) Multiplexed pin whose function is selected by IFCONFIG[1:0].
State
N/A
N/A
Z
Z
I
GPIO8: is a bidirectional I/O port pin.
Reserved. Connect to ground.
Clock for the I
even if no I
Data for the I
if no I
USB Wakeup. If the 8051 is in suspend, asserting this pin starts up
the oscillator and interrupts the 8051 to allow it to exit the suspend
mode. Holding WAKEUP asserted inhibits the EZ-USB chip from
suspending. This pin has programmable polarity, controlled by
WAKEUP[4].
PA0 is a bidirectional I/O port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which is
either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
CLE is the NAND Command Latch Enable signal.
PA1 is a bidirectional I/O port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which is
either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
ALE is the NAND Address Latch Enable signal.
PA2 is a bidirectional I/O port pin.
SLOE is an input-only output enable with programmable polarity
(FIFOPINPOLAR[4]) for the slave FIFOs connected to FD[7:0] or
FD[15:0].
LED1# is the data activity indicator LED sink pin.
OEA[3]
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled by WU2EN
bit (WAKEUP[1]) and polarity set by WU2POL (WAKEUP[4]). If the
8051 is in suspend and WU2EN = 1, a transition on this pin starts
up the oscillator and interrupts the 8051 to allow it to exit the suspend
mode. Asserting this pin inhibits the chip from suspending, if
WU2EN = 1.
LED2# is the chip activity indicator LED sink pin.
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave FIFOs
connected to FD[7:0] or FD[15:0].
WP_NF# is the NAND write-protect control output signal.
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs
connected to FD[7:0] or FD[15:0].
WP_SW# is the NAND write-protect switch input signal.
2
C peripheral is attached.
2
C peripheral is attached.
2
C interface. Connect to VCC with a 2.2K resistor, even
2
C interface. Connect to VCC with a 2.2K resistor,
Description
CY7C68033/CY7C68034
Page 18 of 40