CY7C68034-56LTXI Cypress Semiconductor, CY7C68034-56LTXI Datasheet - Page 20

• Manufacturer Part Number: CY7C68034-56LTXI
• Description: USB Interface IC EZ-USB NX2LP-Flex Flash Controller
• Manufacturer: Cypress Semiconductor

Specifications of CY7C68034-56LTXI

• Rohs: yes
• Product: USB 2.0
• Data Rate: 96 Mbps
• Interface Type: I2C
• Operating Supply Voltage: 3.3 V
• Operating Supply Current: 43 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-56
• Minimum Operating Temperature: - 40 C

Table 8. NX2LP-Flex Pin Descriptions (continued)
Document Number: 001-04247 Rev. *J
QFN Pin
Number
Power and Ground
11, 17,
27, 32,
12, 26,
28, 41,
56-pin
43, 55
53, 56
6, 10
3, 7
46
47
48
49
50
51
52
PD1 or FD[9]
PD2 or FD[10] CE2# or GPIO2
PD3 or FD[11]
PD4 or FD[12] CE4# or GPIO4
PD5 or FD[13] CE5# or GPIO5
PD6 or FD[14] CE6# or GPIO6
PD7 or FD[15] CE7# or GPIO7
AVCC
AGND
VCC
GND
Default Pin
Name
CE3# or GPIO3
Firmware
Usage
NAND
CE1#
N/A
N/A
N/A
N/A
Ground
Ground
Power
Power
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Pin
[6]
Default
I (PD1) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
I (PD2) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
I (PD3) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
I (PD4) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
I (PD5) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
I (PD6) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
I (PD7) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
State
N/A
N/A
N/A
N/A
and EPxFIFOCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
CE1# is a NAND chip enable output signal.
and EPxFIFOCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
CE2# is a NAND chip enable output signal.
GPIO2 is a general purpose I/O signal.
and EPxFIFOCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
CE3# is a NAND chip enable output signal.
GPIO3 is a general purpose I/O signal.
and EPxFIFOCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
CE4# is a NAND chip enable output signal.
GPIO4 is a general purpose I/O signal.
and EPxFIFOCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
CE5# is a NAND chip enable output signal.
GPIO5 is a general purpose I/O signal.
and EPxFIFOCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
CE6# is a NAND chip enable output signal.
GPIO6 is a general purpose I/O signal.
and EPxFIFOCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
CE7# is a NAND chip enable output signal.
GPIO7 is a general purpose I/O signal.
Analog V
provides power to the analog section of the chip.
Analog Ground. Connect to ground with as short a path as
possible.
V
Ground.
CC
. Connect to 3.3 V power source.
CC
. Connect this pin to 3.3 V power source. This signal
Description
CY7C68033/CY7C68034
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