CY7C68034-56LTXI Cypress Semiconductor, CY7C68034-56LTXI Datasheet - Page 32

• Manufacturer Part Number: CY7C68034-56LTXI
• Description: USB Interface IC EZ-USB NX2LP-Flex Flash Controller
• Manufacturer: Cypress Semiconductor

Specifications of CY7C68034-56LTXI

• Rohs: yes
• Product: USB 2.0
• Data Rate: 96 Mbps
• Interface Type: I2C
• Operating Supply Voltage: 3.3 V
• Operating Supply Current: 43 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-56
• Minimum Operating Temperature: - 40 C

Sequence Diagram
Sequence Diagram of a Single and Burst Asynchronous Read
Figure 17
signals during an asynchronous FIFO read. It shows a single
read followed by a burst read.
■
■
■
Document Number: 001-04247 Rev. *J
Note
27. Dashed lines denote signals with programmable polarity.
At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
At t = 2, SLRD is asserted. The SLRD must meet the minimum
active pulse of t
t
SLRD or before SLRD is asserted (that is the SLCS and SLRD
signals must both be asserted to start a valid read condition).
FIFO DATA BUS Not Driven
FIFO POINTER
RDpwh
FIFOADR
FLAGS
SLRD
SLCS
DATA
SLOE
. If SLCS is used then, SLCS must be in asserted with
shows the timing relationship of the SLAVE FIFO
t=0
RDpwl
t=1
N
Driven
Data (X)
Figure 17. Slave FIFO Asynchronous Read Sequence and Timing Diagram
t
SFA
t
SLOE
and minimum deactive pulse width of
OEon
Figure 18. Slave FIFO Asynchronous Read Sequence of Events Diagram
t=2
t
RDpwl
Driven: X
t
XFD
t=3
N
N
t=4
t
RDpwh
t
SLRD
FAH
t
t
OEoff
XFLG
N
N
SLRD
T=0
N+1
N
T=1
SLOE
t
t
SFA
OEon
N
T=2
Not Driven
N+1
t
RDpwl
t
XFD
T=3
SLOE
■
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
Note In burst read mode, during SLOE is assertion, the data bus
is in a driven state and outputs the previous data. After SLRD is
asserted, the data from the FIFO is driven on the data bus (SLOE
must also be asserted) and then the FIFO pointer is
incremented.
The data that is driven, after asserting SLRD, is the updated
data from the FIFO. This data is valid after a propagation delay
of t
is the first valid data read from the FIFO. For data to appear on
the data bus during the read cycle (that is SLRD is asserted),
SLOE MUST be in an asserted state. SLRD and SLOE can
also be tied together.
t
N+1
RDpwh
N+1
XFD
N
T=4
SLRD
from the activating edge of SLRD. In
t
RDpwl
t
N+1
XFD
N+1
T=5
SLRD
t
N+2
RDpwh
N+2
N+1
T=6
CY7C68033/CY7C68034
SLRD
t
RDpwl
t
XFD
N+3
N+2
N+2
T=7
t
t
RDpwh
FAH
SLRD
t
OEoff
[27]
t
N+3
XFLG
N+2
Figure
SLOE
Page 32 of 40
Not Driven
17, data N
N+3