CY7C68034-56LTXI Cypress Semiconductor, CY7C68034-56LTXI Datasheet - Page 19

• Manufacturer Part Number: CY7C68034-56LTXI
• Description: USB Interface IC EZ-USB NX2LP-Flex Flash Controller
• Manufacturer: Cypress Semiconductor

Specifications of CY7C68034-56LTXI

• Rohs: yes
• Product: USB 2.0
• Data Rate: 96 Mbps
• Interface Type: I2C
• Operating Supply Voltage: 3.3 V
• Operating Supply Current: 43 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-56
• Minimum Operating Temperature: - 40 C

Table 8. NX2LP-Flex Pin Descriptions (continued)
Document Number: 001-04247 Rev. *J
QFN Pin
Port B
Number
PORT D
56-pin
39
40
18
19
20
21
22
23
24
25
45
PA6 or
PKTEND
PA7 or FLAGD
or SLCS#
PB0 or FD[0]
PB1 or FD[1]
PB2 or FD[2]
PB3 or FD[3]
PB4 or FD[4]
PB5 or FD[5]
PB6 or FD[6]
PB7 or FD[7]
PD0 or FD[8]
Default Pin
Name
GPIO0 (Input)
GPIO1 (Input)
Firmware
Usage
NAND
CE0#
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Pin
[6]
Default
I (PA6) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
I (PA7) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
I (PB0) Multiplexed pin whose function is selected by IFCONFIG[1:0].
I (PB1) Multiplexed pin whose function is selected by IFCONFIG[1:0].
I (PB2) Multiplexed pin whose function is selected by IFCONFIG[1:0].
I (PB3) Multiplexed pin whose function is selected by IFCONFIG[1:0].
I (PB4) Multiplexed pin whose function is selected by IFCONFIG[1:0].
I (PB5) Multiplexed pin whose function is selected by IFCONFIG[1:0].
I (PB6) Multiplexed pin whose function is selected by IFCONFIG[1:0].
I (PB7) Multiplexed pin whose function is selected by IFCONFIG[1:0].
I (PD0) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
State
bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input used to commit the FIFO packet data to the
endpoint
FIFOPINPOLAR[5].
GPIO1 is a general purpose I/O signal.
and PORTACFG[7] bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status flag signal.
SLCS# gates all other slave FIFO enable/strobes
GPIO0 is a general purpose I/O signal.
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
DD0 is a bidirectional NAND data bus signal.
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
DD1 is a bidirectional NAND data bus signal.
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
DD2 is a bidirectional NAND data bus signal.
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
DD3 is a bidirectional NAND data bus signal.
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
DD4 is a bidirectional NAND data bus signal.
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
DD5 is a bidirectional NAND data bus signal.
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
DD6 is a bidirectional NAND data bus signal.
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
DD7 is a bidirectional NAND data bus signal.
and EPxFIFOCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
CE0# is a NAND chip enable output signal.
and
whose
Description
CY7C68033/CY7C68034
polarity
is
programmable
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