CY7C68034-56LTXI Cypress Semiconductor, CY7C68034-56LTXI Datasheet - Page 33

• Manufacturer Part Number: CY7C68034-56LTXI
• Description: USB Interface IC EZ-USB NX2LP-Flex Flash Controller
• Manufacturer: Cypress Semiconductor

Specifications of CY7C68034-56LTXI

• Rohs: yes
• Product: USB 2.0
• Data Rate: 96 Mbps
• Interface Type: I2C
• Operating Supply Voltage: 3.3 V
• Operating Supply Current: 43 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-56
• Minimum Operating Temperature: - 40 C

Sequence Diagram of a Single and Burst Asynchronous Write
Figure 19
in an asynchronous mode. The diagram shows a single write
followed by a burst write of three bytes and committing the
4-byte-short packet using PKTEND.
■
■
■
At t = 3, deasserting SLWR causes the data to be written from
the data bus to the FIFO and then increments the FIFO pointer.
Document Number: 001-04247 Rev. *J
Note
28. Dashed lines denote signals with programmable polarity.
At t = 0 the FIFO address is applied, insuring that it meets the
setup time of t
(SLCS may be tied low in some applications).
At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of t
t
or before SLWR is asserted.
At t = 2, data must be present on the bus t
deasserting edge of SLWR.
FIFOADR
PKTEND
WRpwh
FLAGS
SLWR
DATA
SLCS
. If the SLCS is used, it must be in asserted with SLWR
shows the timing relationship of the SLAVE FIFO write
t=0
SFA
t
SFA
WRpwl
. If SLCS is used, it must also be asserted
t =1
t
Figure 19. Slave FIFO Asynchronous Write Sequence and Timing Diagram
WRpwl
t=2
and minimum de-active pulse width of
t
SFD
t=3
t
N
t
FDH
WRpwh
t
FAH
t
XFLG
T=0
t
SFA
SFD
T=1
t
before the
WRpwl
T=2
t
SFD
T=3
t
N+1
FDH
t
WRpwh
T=4
The FIFO flag is also updated after t
edge of SLWR.
The same sequence of events are shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
Note In the burst write mode, after SLWR is deasserted, the data
is written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post
incremented.
As shown in
and SLWR is deasserted, the short 4-byte packet can be
committed to the host using the PKTEND. The external device
should be designed to not assert SLWR and the PKTEND signal
at the same time. It should be designed to assert the PKTEND
after SLWR is deasserted and met the minimum de-asserted
pulse width. The FIFOADDR lines are to be held constant during
the PKTEND assertion.
t
WRpwl
T=5
t
SFD
T=6
t
N+2
FDH
t
WRpwh
Figure 19
T=7
t
WRpwl
T=8
t
SFD
T=9
t
t
after the four bytes are written to the FIFO
N+3
WRpwh
FDH
CY7C68033/CY7C68034
[28]
t
XFLG
PEpwl
from the deasserting
t
XFLG
t
PEpwh
t
FAH
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