STA381BWSTR STMicroelectronics, STA381BWSTR Datasheet
STA381BWSTR
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STA381BWSTR Summary of contents
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... STSpeakerSafe – Pre – Checksum engine for filter coefficients – PWM fault self-diagnosis ■ STCompressor Table 1. Order code STA381BWS STA381BWSTR Doc ID 018937 Rev 6 STA381BWS Sound Terminal − Datasheet production data VQFN48 ( mm) 2 DRC) TM protection circuitry ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA381BWS 5.1.2 5.1.3 5.1.4 5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 6.14.2 6.14.3 6.14.4 6.15 Configuration register C (addr 0x13 6.15.1 ...
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STA381BWS 6.22.1 6.23 Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 - 0x46 6.23.1 6.23.2 6.23.3 6.23.4 6.23.5 6.23.6 6.23.7 6.23.8 6.24 User-defined coefficient control registers (addr 0x27 - 0x37) . ...
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Contents 6.27 PLL configuration registers (address 0x52; 0x53; 0x54; 0x55; 0x56; 0x57 6.28 Short-circuit protection mode registers SHOK (address ...
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STA381BWS 7.4.2 7.4.3 7.4.4 7.4.5 7.5 Configuration register E (addr 0x04 113 7.5.1 ...
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Contents 7.11 Dynamic control registers (addr 0x12 - 0x15 129 7.11.1 7.11.2 7.11.3 7.11.4 7.11.5 7.11.6 7.11.7 7.11.8 7.12 User-defined ...
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STA381BWS 7.16.3 7.16.4 7.17 EQ soft volume configuration registers (addr 0x37 - 0x38 145 7.18 Extra volume resolution configuration registers (address 0x3F; 0x40 146 7.19 PLL configuration registers ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA381BWS Table 49. Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 101. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA381BWS Table 153. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA381BWS Figure 49. VQFN48 ( 0.9 mm) package outline ...
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... The serial audio data input interface supports many formats, including the popular IIS format. The STA381BWS is based on an FFX technology from STMicroelectronics. FFX the advanced processor is available for ternary, binary, binary differential and phase shift PWM modulation. The STA381BWS embeds the ternary, binary and binary differential implementations, a subset of the full capability of the FFX The STA381BWS power section consists of four independent half-bridges ...
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STA381BWS 1.1 Block diagram Figure 1. Block diagram Doc ID 018937 Rev 6 Description 17/171 ...
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Pin connections 2 Pin connections 2.1 Connection diagram Figure 2. Pin connections VQFN48 (top view) 18/171 Doc ID 018937 Rev 6 STA381BWS ...
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STA381BWS 2.2 Pin description Table 2. Pin list VQFN 48-pin ...
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Pin connections Table 2. Pin list (continued) VQFN 48-pin 20/171 Name Type EAPD/FFX4B OUTPUT TWARN/FFX4A OUTPUT VREGFILT POWER AGNDPLL POWER MCLK INPUT BICKI ...
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STA381BWS 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Vcc Power supply voltage (VCCxA, VCCxB) VDD_DIG Digital supply voltage VDD3V3 Charge pump and analog path LDO supply VDD3V3CHP Top Operating junction temperature Tstg Storage temperature ...
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Electrical specifications 3.3 Recommended operating conditions Table 5. Recommended operating conditions Symbol Vcc Power supply voltage (VCCxA, VCCxB) VDD_DIG Digital supply voltage VDD3V3 Charge pump and analog path LDO supply VDD3V3CHP Tamb Ambient temperature R Load impedance - line driver ...
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STA381BWS 3.5 Electrical specifications for the power section The specifications given in this section are valid for the operating conditions kHz 384 kHz Table 7. Electrical specifications - power section Symbol Parameter ...
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Electrical specifications Figure 3. Test circuit 3.6 Electrical specifications for the analog section The specifications given in this section are valid for the operating conditions kHz °C, VDD3V3 = 3.3 V, amb Table 8. ...
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STA381BWS 4 Device overview The mentioned hyperlink in this section relates to the default New Map description: New 4.1 Processing data path The whole STA381BWS processing chain is composed of two consecutive sections. In the first one dual-channel processing is ...
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Device overview The second processing stage embeds a mixing block, a biquadratic/crossover filter, a DRC stage, the volume control cut filter and a post scaler. Depending on the device settings, the following configuration and features are available: ● ...
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STA381BWS ● 2.0 output with B divide the channel into two sub-bands, then each sub-band is independently processed by a DRC block. The two bands are then re-composed and fed to the following processing blocks. The crossover frequency is user-selectable. ...
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Device overview 4.2 Input oversampling Figure 4 shows the input oversampling block in front of the main processing. When 32 kHz Fs is used, the default x2 oversampling ratio can be increased to a x3. Activating this feature ...
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STA381BWS 4.3.1 STC block diagram Figure 8. STCompressor Ban d Sp litter Ban d Sp litter The STC takes as input 2 channels and every channel is processed independently (i.e. ...
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Device overview The band splitter filter coefficients have a user-selectable range [-1, 1), [-2, 2) and [-4, 4). The RAM coefficient 0x7 is responsible for these settings according to default value is [-4, 4). Table 9. Coefficients extended-range configuration 0x74h ...
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STA381BWS The STC reacts differently depending on these three parameters ● level meter output value < compressor threshold < limiter threshold: under these circumstances the signal level is small enough to not require any type of limiting/compressing action. The signal ...
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Device overview Figure 11. STCompressor Table 10. Compressor ratio Compressor ratio 32/171 TM behavior as a limiter L.T. L.T. INPUT Doc ID 018937 Rev ...
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STA381BWS 4.3.5 Attenuator The attenuation is characterized by two different phases: attack and release. Given an input signal above the limiter threshold, during the attack phase the STC decreases the gain in order to reach the output level determined by ...
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Device overview 4.3.7 Offset The offset is a user-selectable gain or volume control. When using the STC it is advised to use the offset to tune the output volume instead of the regular volume controls. The offset is located before ...
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STA381BWS Figure 13. Stereo link block diagram Ch 0 – Band 0 From mapper Ch 0 – Band 0 From mapper Ch 0 – Band – Band – Band 0 From mapper Ch 1 ...
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Device overview Table 11. Conversion example Original value (dec) 36/171 +48.00 +24.00 +16.00 +12.00 +06.00 +02.00 +01.00 -01.00 -02.00 -06.00 -12.00 -24.00 -48.00 Doc ID 018937 Rev 6 STA381BWS value (hex) 0x600000 0x300000 0x200000 0x180000 0x0C0000 0x040000 ...
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STA381BWS 4.3.10 Memory map All the control parameters listed in the previous paragraphs are stored in the internal device memory. Please refer to For the programming procedure please refer to control registers (addr 0x27 - the STC coefficients memory. Table ...
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Device overview Table 13. STC band splitter filters memory map Function 38/171 Address Coefficient 0x40 B1/2 0x41 B2 0x42 -A1/2 0x43 -A2 0x44 B0/2 0x45 B1/2 0x46 B2 0x47 -A1/2 0x48 -A2 0x49 B0/2 0x4A B1/2 0x4B B2 0x4C -A1/2 ...
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STA381BWS bus specification The STA381BWS supports the I slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that ...
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I C bus specification the 9th bit time. The byte following the device identification byte is the internal space address. 5.3 Write operation Following the START condition, the master sends a device select code with the RW bit set ...
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STA381BWS 5.4.5 Write mode sequence Figure 14. Write mode sequence BYTE BYTE WRITE WRITE START START MULTIBYTE MULTIBYTE WRITE WRITE START START 5.4.6 Read mode sequence Figure 15. Read mode sequence CURRENT CURRENT DEV-ADDR DEV-ADDR ADDRESS ADDRESS READ READ START ...
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Register description: New Map 6 Register description: New Map Mapping of two registers is available on the STA381BWS, the selection is done by setting register 0x7E bit D7. By default, 0x7E is set to 1 and refers to a map ...
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STA381BWS Table 14. Default register map table: NEW MAP (continued) Addr Name D7 0x25 L2AR L2A3 0x26 L2ATRT L2AT3 0x27 CFADDR 0x28 B1CF1 C1B23 0x29 B1CF2 C1B15 0x2A B1CF3 C1B7 0x2B B2CF1 C2B23 0x2C B2CF2 C2B15 0x2D B2CF3 C2B7 0x2E ...
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Register description: New Map Table 14. Default register map table: NEW MAP (continued) Addr Name D7 CXT75 0x5B MISC1 0x5C RPDNEN MISC2 0x5D LPDP 0x5E BPTH BPTIM 0x60 ZCCFG0 0x61 WTHH ZCCFG1 0x62 ZCCFG2 0x63 ZCCFG3 0x64 ZCCFG4 0x65 HPCFG ...
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STA381BWS 6.1 CLK register (addr 0x00 Table 15. CLK register Bit R/W 7 R/W 6 R/W 5 R/W 4 R/W 0 R/W 6.2 STATUS register (addr 0x01 FAULT DRCCRC NA NA Table 16. STATUS ...
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Register description: New Map 6.3 RESET register (addr 0x02 Reserved Reserved 0 0 Table 17. RESET register Bit R/W 0 R/W After SRESET is written, the last IC acknowledge is skipped and the EAPD bit (reg 0x16 bit ...
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STA381BWS 6.5 MVOL register (addr 0x04 Table 19. Master volume register Bit R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R the volume is below -60 ...
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Register description: New Map 6.7 CH1VOL register (addr 0x06 Table 21. Channel 1 volume register Bit R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R the ...
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STA381BWS 6.9 POST scaler register (addr 0x08 Post scaler is set to POST/128 for both CH1 and CH2. 6.10 OPER register (addr 0x09 Reserved Reserved 0 0 Table 23. OPER register Bit R/W 1 ...
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Register description: New Map Figure 16. OPER = 00 (default value) Figure 17. OPER = 11 Figure 18. OPER = 10 50/171 OUT1A OUT1A Half Half Bridge Bridge Channel 1 Channel 1 Half Half Bridge Bridge OUT1B OUT1B OUT2A OUT2A ...
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STA381BWS Figure 19. OPER = 01 The STA381BWS can be configured to support different output configurations. For each PWM output channel, a PWM slot is defined. A PWM slot is always fs) seconds length. The PWM ...
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Register description: New Map For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage. 2.0 channels, two full-bridges ( ● FFX1A -> OUT1A ● FFX1B -> OUT1B ● FFX2A -> OUT2A ...
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STA381BWS 2.1 channels, two half-bridges + one full-bridge ( ● FFX1A -> OUT1A ● FFX2A -> OUT1B ● FFX3A -> OUT2A ● FFX3B -> OUT2B ● FFX1A -> OUT3A ● FFX1B -> OUT3B ● FFX2A -> OUT4A ● FFX2B -> ...
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Register description: New Map 2.1 channels, two full-bridges + one external full-bridge ( ● FFX1A -> OUT1A ● FFX1B -> OUT1B ● FFX2A -> OUT2A ● FFX2B -> OUT2B ● FFX3A -> OUT3A ● FFX3B -> OUT3B ● EAPD -> ...
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STA381BWS 6.11 FUNCT register (addr 0x0A Reserved CRC 0 0 Table 25. FUNCT register Bit R/W 6 R/W 5 R/W 4 R/W 2 R/W 1 R/W 0 R/W 6.11.1 Dual-band DRC The STA381BWS device provides a dual-band DRC ...
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Register description: New Map with the original signal. Limiter 1 (DRC1) is then used to control the amplitude of the left/right high-frequency components, while limiter 2 (DRC2) is used to control the low- frequency components (see addr 0x43 - 0x46)). ...
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STA381BWS 6.12 HPCFG register (addr 0x10 Reserved Reserved 0 0 Table 26. HPCFG register Bit R/W 0 R/W 6.13 Configuration register A (addr 0x11 FDRB Reserved 0 1 6.13.1 Master clock select Table 27. Master clock ...
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Register description: New Map Table 28. Input sampling rates Input sampling rate fs (kHz) 32, 44.1, 48 88.2, 96 176.4, 192 Note: (*): Clock is BICKI 6.13.2 Interpolation ratio selection Table 29. Internal interpolation ratio Bit R/W 4:3 R/W The ...
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STA381BWS The on-chip STA381BWS power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either overcurrent or thermal). When FAULT is asserted (set to ...
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Register description: New Map 6.14.2 Serial data first bit Table 32. Serial data first bit SAIFB 0 1 Table 33. Support serial audio input formats for MSB-first (SAIFB = 0) BICKI ...
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STA381BWS Table 34. Supported serial audio input formats for LSB-first (SAIFB = 1) BICKI make the STA381BWS work properly, the serial audio interface LRCKI clock must be synchronous to the ...
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Register description: New Map To avoid any audio side effects (like pop noise strongly recommended to soft mute any audio streams flowing into the STA381BWS data path before the desynchronization event happens. At the same time any processing ...
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STA381BWS Table 6: Table 38. Compensating pulse size CSZ[3:0] 0000 0001 … 1111 6.16 Configuration register D (addr 0x14 SME ZDE 0 0 6.16.1 DSP bypass Table 39. DSP bypass Bit R/W 2 R/W Setting the DSPB bit ...
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Register description: New Map 6.16.4 Zero-detect mute enable Table 42. Zero-detect mute enable Bit R/W 6 R/W Refer to 6.32: Enhanced zero-detect mute and input level measurement (address 0x61- 0x65, 0x3F, 0x40, 6.16.5 Submix mode enable Table 43. Submix mode ...
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STA381BWS 6.17.3 PWM speed mode Table 46. PWM speed mode Bit R/W RST 4 R/W 6.17.4 Zero-crossing enable Table 47. Zero-crossing enable Bit R/W RST 6 R/W The ZCE bit enables zero-crossing adjustment. When volume is adjusted on digital zero- ...
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Register description: New Map 6.18.3 LRCK double trigger protection Table 50. LRCK double trigger protection Bit R/W 4 R/W This bit actively prevents double triggering of LRCLK. 6.18.4 Power-down Table 51. IC power-down Bit R/W 7 R/W The PWDN register ...
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STA381BWS Table 53. Line output configuration LOC[1: Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 ...
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Register description: New Map 6.19.2 Channel 3 / line output volume (addr 0x1B The volume structure of the STA381BWS consists of individual volume registers for each channel and a master volume register that provides an offset ...
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STA381BWS 6.20 Audio preset registers (0x1D XO3 XO2 0 0 6.20.1 AM interference frequency switching Table 56. AM interference frequency switching bits Bit R/W 0 R/W Table 57. Audio preset AM switching frequency selection AMAM[2:0] 000 001 010 ...
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Register description: New Map Table 59. Bass management crossover frequency XO[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 6.21 Channel configuration registers (addr 0x1F - 0x21 Reserved Reserved 0 ...
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STA381BWS 6.21.2 EQ bypass EQ control can be bypassed on a per-channel basis for channels 1 and control is bypassed on a given channel, the prescale and all filters (biquads, bass, treble in any combination) are bypassed ...
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Register description: New Map 6.21.6 Output mapping Output mapping can be performed on a per-channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing ...
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STA381BWS 6.23 Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 - 0x46) 6.23.1 Limiter 1 attack/release rate (L1AR addr 0x23 L1A3 L1A2 0 1 6.23.2 Limiter 1 attack/release threshold (L1ATRT addr 0x24 L1AT3 L1AT2 ...
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Register description: New Map ERTHx[6:0]. Setting the ERTHx[7] bits to 1 automatically selects the anticlipping mode. The release of the limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume/limiter block is ...
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STA381BWS Figure 25. Basic limiter and volume flow diagram Gain / Vo lume Table 67. Limiter attack rate as a function of LxA bits LxA[3:0] Attack rate dB/ms 0000 0001 0010 0011 0100 0101 0110 0111 1000 ...
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Register description: New Map Anticlipping mode Table 69. Limiter attack threshold as a function of LxAT bits (AC mode) LxAT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 76/171 AC (dB relative ...
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STA381BWS Dynamic range compression mode Table 71. Limiter attack threshold as a function of LxAT bits (DRC mode) LxAT[3:0] DRC (dB relative to volume) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ...
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Register description: New Map 6.23.7 Limiter 2 extended attack threshold (addr 0x45 EATHEN2 EATH2[ The extended attack threshold value is determined as follows: attack threshold = -12 + EATH2 / 4 To enable this feature, the ...
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STA381BWS 6.24.5 Coefficient b2 data register bits 23: C2B23 C2B22 0 0 6.24.6 Coefficient b2 data register bits 15 C2B15 C2B14 0 0 6.24.7 Coefficient b2 data register bits 7 C2B7 C2B6 0 0 ...
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Register description: New Map 6.24.12 Coefficient a2 data register bits 15 C4B15 C4B14 0 0 6.24.13 Coefficient a2 data register bits 7 C4B7 C4B6 0 0 6.24.14 Coefficient b0 data register bits 23: C5B23 ...
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STA381BWS Reading a coefficient from RAM 1. Write 6 bits of the address Write 1 to the R1 bit Read the top 8 bits of the coefficient Read the middle 8 ...
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Register description: New Map Writing a set of coefficients to RAM 1. Write 6 bits of the starting address Write the top 8 bits of coefficient Write the middle 8 bits of coefficient ...
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STA381BWS 6.24.18 User-defined EQ The STA381BWS can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation ...
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Register description: New Map default, all post-scale factors are set to 0x7FFFFF. When line output is being used, channel-3 post-scale will affect both channels 3 and 4. Table 73. RAM block for biquads, mixing, scaling and bass management Index (decimal) ...
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STA381BWS 6.25 Fault-detect recovery constant registers (addr 0x3C - 0x3D FDRC15 FDRC14 FDRC7 FDRC6 0 0 The FDRC bits specify the 16-bit fault-detect recovery time delay. When FAULT is asserted, the TRISTATE output is ...
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Register description: New Map Table 76. Extended attack rate, limiter 2 XAR2 0 1 6.26.3 Extended biquad selector Bass and treble controls can be configured as user-defined filters when the equalization coefficients link is activated (BQL = 1) and the ...
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STA381BWS 6.27 PLL configuration registers (address 0x52; 0x53; 0x54; 0x55; 0x56; 0x57 PLL_DITH[1: PLL_DPD PLL_FCT Reserved Reserved Reserved ...
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Register description: New Map Table 81. PLL register 0x54 bits Bit R/W RST 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Table 82. PLL register 0x55 bits Bit R/W RST 7 R/W ...
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STA381BWS Table 84. PLL register 0x57 bits Bit R/W 3 R/W 2 R/W 1 R/W 0 R/W 6.28 Short-circuit protection mode registers SHOK (address 0x58 reserved reserved NA NA The following power bridge pins short-circuit protections are implemented ...
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Register description: New Map Figure 26. Short-circuit detection timing diagram (no short detected) EAPD OUT1A OUT1B OUT2A OUT2B GNDSH] VCCSH OUTSH] In Figure 26 the short protection timing diagram is shown. The time information is expressed in clock cycles, where ...
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STA381BWS Table 85. Coefficients extended range configuration CEXT_Bx[ this case the user can decide, for each filter stage, the right coefficient range. Note that for a given biquad the same range will be applied to ...
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Register description: New Map 6.30.3 Channel PWM enable (CPWMEN) bit This bit, when set, activates a mute output in case the volume reaches a value lower than -76 dBFS. 6.30.4 External amplifier hardware pin enabler (LPDP, LPD LPDE) bits Pin ...
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STA381BWS Table 87. PNDLSL bits configuration PNDLSL[2] PNDLSL[ 6.30.6 Short-circuit check enable bit This bit, when enabled, will activate the short-circuit checks before any power bridge activation (EAPD bit 0->1). See section ...
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Register description: New Map 6.32 Enhanced zero-detect mute and input level measurement (address 0x61-0x65, 0x3F, 0x40, 0x6F WTHH WTHL N/A N N/A N N/A N N/A N/A The ...
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STA381BWS Table 89. Zero-detect hysteresis HSEL[1: The thresholds and hysteresis table above can be overridden and the low-level threshold and high-level threshold can be set by the MTH[21:0] bits. To activate the manual thresholds the FINETH ...
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Register description: New Map 6.33 Headphone/Line out configuration register (address 0x66 HPLN Reserved 0 0 Table 91. Headphone/Line out configuration bits Bit R/W 7 R 96/171 D5 D4 Reserved Reserved ...
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STA381BWS 6.34 F3XCFG (address 0x69; 0x6A F3XLNK reserved F3X_FAULT reserved 1 1 Table 92. F3X configuration register 1 Bit R/W 7 R/W Table 93. F3X configuration register 2 Bit R R/W ...
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Register description: New Map 6.35 STCompressor 0x6C) Table 94. Register STCCFG0 D7 D6 Reserved Reserved 0 0 Table 95. STCCFG0 register Bit R/W 2 R/W Table 96. Register STCCFG1 D7 D6 Reserved Reserved 0 0 Table 97. STCCFG1 register Bit ...
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STA381BWS The charge pump can be synchronized with the PWM frame in order to minimize the crosstalk between the charge pump and the PWM waveform. This functionality cannot be activated when the PWMS bit (address 0x15 bit D4) is set ...
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Register description: New Map XCAUTO XCRES 0 0 The STA381BWS implements an automatic CRC computation for the biquad and MDRC/XOver coefficient memory 0x27 will be bit XORed to obtain the BQCHKE checksum, while cells ...
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STA381BWS else { BC_RES = 1;// Checksum error detected, set the error bit } ● Wait until the BCRES bit goes to 0, meaning that the checksum result bit has started to be updated and everything is ok. Time-out of ...
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Register description: New Map Direct single-write procedure 1. Set reg 0x7E bit and bit enable the direct RAM access in single-write mode. 2. Write the coefficient value to the device using an I ...
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STA381BWS 7 Register description: Sound Terminal compatibility To keep compatibility with previous Sound Terminal devices, the 0x7E bit D7 must be set to 0 after device turn-on and after any reset (via SW or via external pin). Missing addresses are ...
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Register description: Sound Terminal compatibility 2 Table 100 registers summary (continued) 1F A1CF3 C3B7 20 A2CF1 C4B23 21 A2CF2 C4B15 22 A2CF3 C4B7 23 B0CF1 C5B23 24 B0CF2 C5B15 25 B0CF3 C5B7 26 CFUD 2B FDRC1 FDRC15 2C ...
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STA381BWS 2 Table 100 registers summary (continued) 4C MISC2 LPDP 4D BPTH 4E BADPWM BP4B 4F BPTIM 50 ZCCFG0 WTHH 51 ZCCFG1 52 ZCCFG2 53 ZCCFG3 54 ZCCFG4 55 HPCFG HPLN 58 F3XCFG1 F3XLNK F3X_ 59 F3XCFG2 FAULT ...
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Register description: Sound Terminal compatibility 7.1 Configuration register A (addr 0x00 FDRB Reserved 0 1 7.1.1 Master clock select Table 101. Master clock select Bit R/W 0 R/W 1 R/W 2 R/W The STA381BWS supports sampling rates of ...
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STA381BWS 7.1.2 Interpolation ratio select Table 103. Internal interpolation ratio Bit R/W 4:3 R/W The STA381BWS has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates by either 3 times ...
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Register description: Sound Terminal compatibility 7.2 Configuration register B (addr 0x01 C2IM C1IM 1 0 7.2.1 Serial data interface The STA381BWS audio serial input was designed to interface with standard digital audio components and to accept a number ...
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STA381BWS Table 108. Support serial audio input formats for MSB-first (SAIFB = 0) BICKI Register description: Sound Terminal compatibility SAI [3:0] SAIFB 2 0000 15-bit data 0001 0 ...
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Register description: Sound Terminal compatibility Table 109. Supported serial audio input formats for LSB-first (SAIFB = 1) BICKI make the STA381BWS work properly, the serial audio interface LRCKI clock must ...
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STA381BWS happens. At the same time any processing related to the I only after the serial audio interface and the internal PLL are synchronous again. Note: Any mute or volume change causes some delay in the completion of the I ...
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Register description: Sound Terminal compatibility 7.3 Configuration register C (addr 0x02 Reserved Reserved 1 0 7.3.1 FFX compensating pulse size register Table 112. FFX compensating pulse size bits Bit R/W 2 R/W 3 R/W 4 R/W 5 R/W ...
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STA381BWS 7.4.2 Post-scale link Table 115. Post-scale link Bit R/W 3 R/W Post-scale functionality can be used for power supply error correction. For multi-channel applications running off the same power supply, the post-scale values can be linked to the value ...
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Register description: Sound Terminal compatibility 7.5.1 Noise-shaper bandwidth selection Table 119. Noise-shaper bandwidth selection Bit R/W RST 2 R/W 7.5.2 AM mode enable Table 120. AM mode enable Bit R/W RST 3 R/W The STA381BWS features an FFX processing mode ...
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STA381BWS 7.6 Configuration register F (addr 0x05 EAPD PWDN 0 1 7.6.1 Output configuration Table 124. Output configuration Bit R/W 0 R/W 1 R/W Table 125. Output configuration engine selection OCFG[1:0] 2-channel (full-bridge) power, 2-channel data-out: 1A/1B → ...
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Register description: Sound Terminal compatibility Figure 31. OCFG = 00 (default value) Figure 32. OCFG = 01 Figure 33. OCFG = 10 116/171 OUT1A OUT1A Half Half Bridge Bridge Channel 1 Channel 1 Half Half Bridge Bridge OUT1B OUT1B OUT2A ...
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STA381BWS Figure 34. OCFG = 11 The STA381BWS can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. A PWM slot is always fs) seconds length. The PWM ...
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Register description: Sound Terminal compatibility For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage: 2.0 channels, two full-bridges (OCFG = 00) ● FFX1A -> OUT1A ● FFX1B -> OUT1B ● ...
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STA381BWS 2.1 channels, two half-bridges + one full-bridge (OCFG = 01) ● FFX1A -> OUT1A ● FFX2A -> OUT1B ● FFX3A -> OUT2A ● FFX3B -> OUT2B ● FFX1A -> OUT3A ● FFX1B -> OUT3B ● FFX2A -> OUT4A ● ...
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Register description: Sound Terminal compatibility 2.1 channels, two full-bridges + one external full-bridge (OCFG = 10) ● FFX1A -> OUT1A ● FFX1B -> OUT1B ● FFX2A -> OUT2A ● FFX2B -> OUT2B ● FFX3A -> OUT3A ● FFX3B -> OUT3B ...
Page 121
STA381BWS 7.6.2 Invalid input detect mute enable Table 126. Invalid input detect mute enable Bit R/W RST 2 R/W Setting the IDE bit enables this function, which looks at the input I mutes if the signals are perceived as invalid. ...
Page 122
Register description: Sound Terminal compatibility The EAPD register directly disables/enables the internal power circuitry. When EAPD = 0, the internal power section is placed in a low-power state (disabled). This register also controls the EAPD/FFX4B output pin when OCFG = ...
Page 123
STA381BWS Bit R/W 1 R/W 0 R/W 7.7.2 Master volume register 7.7.3 Channel 1 volume 7.7.4 Channel 2 volume 7.7.5 Channel 3 / line output volume D7 D6 ...
Page 124
Register description: Sound Terminal compatibility provided via the master volume register, any channel whose total volume is less than - muted. All changes in volume take place at zero-crossings when ZCE = 1 (addr 0x04 per-channel ...
Page 125
STA381BWS 7.8.2 AM interference frequency switching Table 135. AM interference frequency switching bits Bit R/W 0 R/W Table 136. Audio preset AM switching frequency selection AMAM[2:0] 000 001 010 011 100 101 110 7.8.3 Bass management ...
Page 126
Register description: Sound Terminal compatibility Table 138. Bass management crossover frequency XO[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 7.9 Channel configuration registers (addr 0x0E - 0x10 C1OM1 C1OM0 ...
Page 127
STA381BWS 7.9.2 EQ bypass EQ control can be bypassed on a per-channel basis for channels 1 and control is bypassed on a given channel, the prescale and all filters (biquads, bass, treble in any combination) are bypassed ...
Page 128
Register description: Sound Terminal compatibility 7.9.6 Output mapping Output mapping can be performed on a per-channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three ...
Page 129
STA381BWS 7.11 Dynamic control registers (addr 0x12 - 0x15) 7.11.1 Limiter 1 attack/release rate D7 D6 L1A3 L1A2 0 1 7.11.2 Limiter 1 attack/release threshold D7 D6 L1AT3 L1AT2 0 1 7.11.3 Limiter 2 attack/release rate D7 D6 L2A3 L2A2 ...
Page 130
Register description: Sound Terminal compatibility automatically selects the anticlipping mode. The release of the limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume/limiter block is passed through an RMS filter. The ...
Page 131
STA381BWS Figure 39. Basic limiter and volume flow diagram Gain / Vo lume Table 146. Limiter attack rate as a function of LxA bits LxA[3:0] Attack rate dB/ms 0000 0001 0010 0011 0100 0101 0110 0111 1000 ...
Page 132
Register description: Sound Terminal compatibility Anticlipping mode Table 148. Limiter attack threshold as a function of LxAT bits (AC mode) LxAT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 132/171 AC (dB ...
Page 133
STA381BWS Dynamic range compression mode Table 150. Limiter attack threshold as a function of LxAT bits (DRC mode) LxAT[3:0] DRC (dB relative to volume) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ...
Page 134
Register description: Sound Terminal compatibility 7.11.7 Limiter 2 extended attack threshold (addr 0x34 EATHEN2 EATH2[ The extended attack threshold value is determined as follows: attack threshold = -12 + EATH2 / 4 To enable this feature, ...
Page 135
STA381BWS 7.12.5 Coefficient b2 data register bits 23: C2B23 C2B22 0 0 7.12.6 Coefficient b2 data register bits 15 C2B15 C2B14 0 0 7.12.7 Coefficient b2 data register bits 7 C2B7 C2B6 0 0 ...
Page 136
Register description: Sound Terminal compatibility 7.12.12 Coefficient a2 data register bits 15 C4B15 C4B14 0 0 7.12.13 Coefficient a2 data register bits 7 C4B7 C4B6 0 0 7.12.14 Coefficient b0 data register bits 23: ...
Page 137
STA381BWS Reading a coefficient from RAM 1. Write 6 bits of the address Write 1 to the R1 bit Read the top 8 bits of the coefficient Read the middle 8 ...
Page 138
Register description: Sound Terminal compatibility Writing a set of coefficients to RAM 1. Write 6 bits of the starting address Write the top 8 bits of coefficient Write the middle 8 bits of ...
Page 139
STA381BWS 7.12.18 User-defined EQ The STA381BWS can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation ...
Page 140
Register description: Sound Terminal compatibility default, all post-scale factors are set to 0x7FFFFF. When line output is being used, channel-3 post-scale will affect both channels 3 and 4. Table 152. RAM block for biquads, mixing, scaling and bass management Index ...
Page 141
STA381BWS 7.13 Fault-detect recovery constant registers (addr 0x2B - 0x2C FDRC15 FDRC14 FDRC7 FDRC6 0 0 The FDRC bits specify the 16-bit fault-detect recovery time delay. When FAULT is asserted, the TRISTATE output is ...
Page 142
Register description: Sound Terminal compatibility 7.16 Extended configuration register (addr 0x36 MDRCE Reserved 0 0 The extended configuration register provides access to B 7.16.1 Dual-band DRC The STA381BWS device provides a dual-band DRC (B data path, as depicted ...
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STA381BWS Sub-band decomposition The sub-band decomposition for B The cutoff frequency can be programmed in two ways, using the XO bits in register 0x0C, or using the “user programmable” mode (coefficients stored in RAM addresses 0x28 to 0x31). For the ...
Page 144
Register description: Sound Terminal compatibility 7.16.3 Extended attack rate The attack rate shown in on both limiters. Table 155. Extended attack rate, limiter 1 XAR1 0 1 Table 156. Extended attack rate, limiter 2 XAR2 0 1 7.16.4 Extended BIQUAD ...
Page 145
STA381BWS 7.17 EQ soft volume configuration registers (addr 0x37 - 0x38 Reserved Reserved Reserved Reserved 0 0 The soft volume update has a fixed rate by default. Using register 0x37 and 0x38 it is ...
Page 146
Register description: Sound Terminal compatibility 7.18 Extra volume resolution configuration registers (address 0x3F; 0x40 VRESEN VRESTG reserved reserved 0 0 Extra volume resolution allows fine volume tuning by steps of 0.125 dB. The feature ...
Page 147
STA381BWS Two different behaviors can be configured by the VRESTG bit. If VRESTG=’0’ the CxVR contribution will be applied immediately after the corresponding bits are written. If VRESTG=’1’ the CxVR bits will be effective on channel volume ...
Page 148
Register description: Sound Terminal compatibility The output PLL frequency formula is: where Fin is the input clock frequency from the pad. Table 164. PLL factors PLL parameter FRAC IDIV NDIV Table 165. PLL register 0x43 bits Bit R/W 7 R/W ...
Page 149
STA381BWS Table 167. PLL register 0x45 bits Bit R/W 5 R/W 4 R/W 3 R/W 2 R/W 0 R/W Table 168. PLL register 0x46 bits Bit R 7.20 Short-circuit protection mode registers ...
Page 150
Register description: Sound Terminal compatibility To be noted that once the check is performed, and the tristate released, the short protection is not active anymore until the next EAPD 0->1 toggling which means that shorts that happened during normal operation ...
Page 151
STA381BWS 7.21 Extended coefficient range up to -4...4 (address 0x49, 0x4A CEXT_B4[1] CEXT_B4[ reserved reserved 0 0 Biquads from have in the STA381BWS the possibility to extend the coefficient range from ...
Page 152
Register description: Sound Terminal compatibility 7.22.2 Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5) A fade-out procedure is started in the STA381BWS once the PWDN function is enabled, and after 13 million clock cycles (PLL internal frequency) the bridge ...
Page 153
STA381BWS Figure 43. Alternate function for INTLINE pin “is the d evice erd ?” 7.22.5 Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C, bit D4, D3, D2) As per Section 7.22.2, the assertion of PWDN ...
Page 154
Register description: Sound Terminal compatibility 7.23 Bad PWM detection registers (address 0x4D, 0x4E, 0x4F BPTH[5] BPTH[ BP4B BP4A BPTIM[7] BPTIM[ The STA381BWS implements a detection on the PWM ...
Page 155
STA381BWS 7.24 Enhanced zero-detect mute and input level measurement (address 0x50-0x54, 0x2E, 0x2F and 0x5E WTHH WTHL N/A N N/A N N/A N N/A N/A The STA381BWS implements ...
Page 156
Register description: Sound Terminal compatibility Table 172. Zero-detect threshold ZMTH[2:0] 000 001 010 011 100 101 110 111 Table 173. Zero-detect hysteresis HSEL[1: The above thresholds and hysteresis table can be overridden and the low-level threshold ...
Page 157
STA381BWS Table 174. Manual threshold register 0x2E, 0x2F and 0x5E D7 D6 ReservedT Reserved 7.25 Headphone/Line out configuration register (address 0x55 HPLN Reserved 0 0 Table 175. Headphone/Line ...
Page 158
Register description: Sound Terminal compatibility 7.26 F3XCFG (address 0x58; 0x59 F3XLNK Reserved F3X_FAULT Reserved NA 1 Table 176. F3X configuration register 1 Bit R/W 7 R/W Table 177. F3X configuration register 2 Bit R/W ...
Page 159
STA381BWS 7.27 STCompressor 0x5B reserved LIM_BYP reserved reserved 0 0 Table 178. STCompressor Bit R/W 6 R/W 5 R R/W Table 179. STCompressor Bit R ...
Page 160
Register description: Sound Terminal compatibility 7.28 Charge pump synchronization (address 0x5F Reserved Reserved 0 0 Table 180. Charge pump sync configuration bits Bit R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W The charge ...
Page 161
STA381BWS 7.29 Coefficient RAM CRC protection (address 0x60-0x6C BQCKE[7] BQCKE[ BQCKE[15] BQCKE[14 BQCKE[23] BQCKE[22 XCCKE[7] XCCKE[ XCCKE[15] XCCKE[14 ...
Page 162
Register description: Sound Terminal compatibility The STA381BWS implements an automatic CRC computation for the biquad and MDRC/XOver coefficient memory. Memory cell contents from address 0x00 to 0x27 will be bit XORed to obtain the BQCHKE checksum, while cells from 0x28 ...
Page 163
STA381BWS 7.30 MISC3 (address 0x6E reserved reserved 0 0 Table 181. Misc register 3 Bit R/W 2 R/W After SRESET is written, the last IC acknowledge is skipped and the EAPD bit (reg 0x16 bit D7) is set ...
Page 164
Applications 8 Applications 8.1 Application schemes The following figures illustrate typical application schemes for the STA381BWS. The line/headphone out can be fed either with an external analog source F3X output, allowing to have the audio content coming from the digital ...
Page 165
STA381BWS Figure 45. F3X (from SAI) source to line/headphone out application scheme Note: For further information, please refer to application note AN3959, 2.0-channel demonstration board based on the STA381BW and STA381BWS. STA381BWS Doc ID 018937 Rev 6 Applications 165/171 ...
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Applications Figure 46. F3X auxiliary analog output Note: For further information, please refer to application note AN3959, 2.0-channel demonstration board based on the STA381BW and STA381BWS. 8.2 Headphone and 2 Vrms line out Figure 47. Headphone and line out block ...
Page 167
STA381BWS Besides the digital input to the power output path, a line in to the headphone / 2Vrms line out path is provided. The headphone and line out block diagram is shown in overall gain is determined by the external ...
Page 168
Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...
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STA381BWS Table 183. VQFN48 ( 0.9 mm) package dimensions Reference (pad pitch) L1 aaa bbb ddd eee fff ccc mm Min. Typ. 0.80 0.90 0 6.90 7.00 5.65 ...
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Revision history 10 Revision history Table 184. Document revision history Date Revision 08-Jun-2011 1 Initial release 28-Jun-2011 2 Removed TQFP64 package option Added note to 02-Sep-2011 3 Section 8.2: Headphone and 2 Vrms line Updated names of pin 32 and ...
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... STA381BWS Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...