STA381BWSTR STMicroelectronics, STA381BWSTR Datasheet - Page 65

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STA381BWSTR

Manufacturer Part Number
STA381BWSTR
Description
Audio DSPs Sound Terminal 2.1 High EFF Dig Audio
Manufacturer
STMicroelectronics
Datasheet

Specifications of STA381BWSTR

Product Category
Audio DSPs
Rohs
yes
Operating Supply Voltage
4.5 V to 25.5 V
Operating Temperature Range
0 C to + 150 C
Mounting Style
SMD/SMT
Package / Case
VQFN-48
Snr
100 dB

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STA381BWS
6.17.3
6.17.4
6.18
6.18.1
6.18.2
PWM speed mode
Table 46.
Zero-crossing enable
Table 47.
The ZCE bit enables zero-crossing adjustment. When volume is adjusted on digital zero-
crossing, no clicks are audible
Configuration register F (addr 0x16)
Invalid input detect mute enable
Table 48.
Setting the IDE bit enables this function, which looks at the input I
mutes if the signals are perceived as invalid.
Binary output mode clock loss detection
Table 49.
This bit detects loss of input MCLK in binary mode and will output 50% duty cycle.
Bit
Bit
Bit
Bit
4
6
2
3
EAPD
D7
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM speed mode
Zero-crossing enable
Invalid input detect mute enable
Binary output mode clock loss detection
PWDN
D6
RST
RST
1
0
0
RST
RST
1
1
Reserved
Name
PWMS
ZCE
D5
Name
0
Doc ID 018937 Rev 6
Name
Name
BCLE
IDE
‘1’: Volume adjustment only occurs at digital zero-crossing
‘0’: Volume adjustment occur immediately
LDTE
D4
1
0: Normal speed (384 kHz) all channels
1: Odd speed (341.3 kHz) all channels. Not suitable for
binary BTL mode.
Setting of 1 enables the automatic invalid input
detect mute
Binary output mode clock loss detection enable
BCLE
D3
1
Register description: New Map
Description
Description
IDE
Description
Description
D2
1
2
S data and automatically
Reserved
D1
Reserved
D0
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