STA381BWSTR STMicroelectronics, STA381BWSTR Datasheet - Page 93

• Manufacturer Part Number: STA381BWSTR
• Description: Audio DSPs Sound Terminal 2.1 High EFF Dig Audio
• Manufacturer: STMicroelectronics

Specifications of STA381BWSTR

• Product Category: Audio DSPs
• Rohs: yes
• Operating Supply Voltage: 4.5 V to 25.5 V
• Operating Temperature Range: 0 C to + 150 C
• Mounting Style: SMD/SMT
• Package / Case: VQFN-48
• Snr: 100 dB

STA381BWS
6.30.6
6.31
Table 87.
Short-circuit check enable bit
This bit, when enabled, will activate the short-circuit checks before any power bridge
activation (EAPD bit 0->1). See section
SHOK (address 0x58)
Bad PWM detection registers (address 0x5E, 0x5F, 0x60)
The STA381BWS implements a detection on PWM outputs able to verify if the output signal
has no zero-crossing in a configurable time window. This check can be useful to detect the
DC level in the PWM outputs. To be noted that the checks are performed on logic level PWM
(i.e. not the power bridge ones, nor the PWM on DDX3 and DDX4 IOs).
In case of ternary modulation, the detection threshold is computed as:
If the measured PWM duty cycle is detected greater than or equal to TH for more than
BPTIM PWM periods, the corresponding PWM bit will be set in register 0x01.
In case of binary modulation, there are two thresholds:
In this case if the measured PWM duty cycle is outside the TH1-TH2 range for more than
BPTIM PWM periods, the corresponding bit will be set in register 0x4E.
PNDLSL[2]
BPTIM[7]
BPTH[5]
D7
D7
0
0
0
0
0
0
1
1
1
1
TH=[(BPTH*2+1)/128]*100%
TH1=[(64+BPTH)/128]*100%
TH2=[(64-BPTH)/128]*100%
PNDLSL bits configuration
BPTIM[6]
BPTH[4]
PNDLSL[1]
D6
D6
0
1
0
0
1
1
0
0
1
1
for more details.
BPTIM[5]
BPTH[3]
D5
D5
1
0
Doc ID 018937 Rev 6
PNDLSL[2]
0
1
0
1
0
1
0
1
BPTIM[4]
BPTH[2]
D4
D4
Section 6.28: Short-circuit protection mode registers
1
1
BPTIM[3]
BPTH[1]
Default time (13M PLL clock cycles)
D3
D3
0
1
Default time divided by 128
Default time divided by 16
Default time divided by 32
Default time divided by 64
Default time divided by 2
Default time divided by 4
Default time divided by 8
Register description: New Map
BPTIM[2]
BPTH[0]
Fade-out time
D2
D2
0
1
BPTIM[1]
reserved
D1
D1
1
1
BPTIM[0]
reserved
D0
D0
0
0
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