STA381BWSTR STMicroelectronics, STA381BWSTR Datasheet - Page 141

• Manufacturer Part Number: STA381BWSTR
• Description: Audio DSPs Sound Terminal 2.1 High EFF Dig Audio
• Manufacturer: STMicroelectronics

Specifications of STA381BWSTR

• Product Category: Audio DSPs
• Rohs: yes
• Operating Supply Voltage: 4.5 V to 25.5 V
• Operating Temperature Range: 0 C to + 150 C
• Mounting Style: SMD/SMT
• Package / Case: VQFN-48
• Snr: 100 dB

STA381BWS
7.13
7.14
7.15
Fault-detect recovery constant registers (addr 0x2B - 0x2C)
The FDRC bits specify the 16-bit fault-detect recovery time delay. When FAULT is asserted,
the TRISTATE output is immediately asserted low and held low for the time period specified
by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The
default value of 0x300C gives approximately 1 sec.
0x0000 is a reserved value.
Device status register (addr 0x2D)
This read-only register provides fault and thermal-warning status information from the power
control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault
or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked.
Table 153. Status register bits
EQ coefficients configuration register (addr 0x31)
The XOB bit can be used to bypass the crossover filters. Logic 1 means that the function is
not active. In this case, the high-pass crossover filter works as a pass-through on the data
path (b=0, all the other coefficients at logic 0 ) while the low-pass filter is configured to have
zero signal on channel 3 data processing (all the coefficients are at logic 0)
Bit
FDRC15
7
6
FDRC7
PLLUL
XOB
D7
D7
D7
D7
0
0
0
R/W
R
R
Reserved
FDRC14
FDRC6
FAULT
D6
D6
D6
D6
0
0
0
RST
-
-
Reserved
Reserved
FDRC13
FDRC5
D5
D5
D5
D5
1
0
0
Doc ID 018937 Rev 6
PLLUL
FAULT
Name
Register description: Sound Terminal compatibility
Reserved
Reserved
FDRC12
FDRC4
D4
D4
D4
D4
1
0
0
0: PLL locked
1: PLL not locked
0: fault detected on power bridge
1: normal operation
Reserved
Reserved
FDRC11
FDRC3
D3
D3
D3
D3
0
1
0
Reserved
Reserved
FDRC10
FDRC2
Description
D2
D2
D2
D2
0
1
0
Reserved
Reserved
FDRC9
FDRC1
D1
D1
D1
D1
0
0
0
.
Reserved
Reserved
FDRC8
FDRC0
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D0
D0
D0
D0
0
0
0