STA381BWSTR STMicroelectronics, STA381BWSTR Datasheet - Page 73

• Manufacturer Part Number: STA381BWSTR
• Description: Audio DSPs Sound Terminal 2.1 High EFF Dig Audio
• Manufacturer: STMicroelectronics

Specifications of STA381BWSTR

• Product Category: Audio DSPs
• Rohs: yes
• Operating Supply Voltage: 4.5 V to 25.5 V
• Operating Temperature Range: 0 C to + 150 C
• Mounting Style: SMD/SMT
• Package / Case: VQFN-48
• Snr: 100 dB

STA381BWS
6.23
6.23.1
6.23.2
6.23.3
6.23.4
Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 -
0x46)
Limiter 1 attack/release rate (L1AR addr 0x23)
Limiter 1 attack/release threshold (L1ATRT addr 0x24)
Limiter 2 attack/release rate ( L2AR addr 0x25)
Limiter 2 attack/release threshold ( L2 ATRT addr 0x26)
The STA381BWS includes two independent limiter blocks. The purpose of the limiters is to
automatically reduce the dynamic range of a recording to prevent the outputs from clipping
in anticlipping mode or to actively reduce the dynamic range for a better listening
environment such as a nighttime listening mode which is often needed for DVDs. The two
modes are selected via the DRC bit in
channel can be mapped to either limiter or not mapped, meaning that the channel will clip
when 0 dBfs is exceeded. Each limiter looks at the present value of each channel that is
mapped to it, selects the maximum absolute value of all these channels, performs the
limiting algorithm on that value, and then, if needed, adjusts the gain of the mapped
channels in unison.
The limiter attack thresholds are determined by the LxAT registers if the EATHx[7] (bit D7 of
register 0x43 or 0x45) bits are set to 0, else the thresholds are determined by EATHx[6:0]. It
is recommended in anticlipping mode to set this to 0 dBfs, which corresponds to the
maximum unclipped output power of an FFX amplifier. Since gain can be added digitally
within the STA381BWS it is possible to exceed 0 dBfs or any other LxAT setting. When this
occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the
gain is reduced when the attack threshold is exceeded is dependent upon the attack rate
register setting for that limiter. Gain reduction occurs on a peak-detect algorithm. Setting the
EATHx[7] bits to 1 selects the anticlipping mode.
The limiter release thresholds are determined by the LxRT registers if the ERTHx[7] (bit D7
of register 0x44 or 0x46) bits are set to 0, else the thresholds are determined by
L1AT3
L2AT3
L1A3
L2A3
D7
D7
D7
D7
0
0
0
0
L1AT2
L2AT2
L1A2
L2A2
D6
D6
D6
D6
1
1
1
1
L1AT1
L2AT1
L1A1
L2A1
D5
D5
D5
D5
1
1
1
1
Doc ID 018937 Rev 6
L1AT0
L2AT0
L1A0
L2A0
Section 6.11: FUNCT register (addr
D4
D4
D4
D4
0
0
0
0
L1RT3
L2RT3
L1R3
L2R3
D3
D3
D3
D3
1
1
1
1
Register description: New Map
L1RT2
L2RT2
L1R2
L2R2
D2
D2
D2
D2
0
0
0
0
L1RT1
L2RT1
L1R1
L2R1
D1
D1
D1
D1
1
0
1
0
0x0A). Each
L1RT0
L2RT0
L1R0
L2R0
D0
D0
D0
D0
0
1
0
1
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