STA381BWSTR STMicroelectronics, STA381BWSTR Datasheet - Page 147

• Manufacturer Part Number: STA381BWSTR
• Description: Audio DSPs Sound Terminal 2.1 High EFF Dig Audio
• Manufacturer: STMicroelectronics

Specifications of STA381BWSTR

• Product Category: Audio DSPs
• Rohs: yes
• Operating Supply Voltage: 4.5 V to 25.5 V
• Operating Temperature Range: 0 C to + 150 C
• Mounting Style: SMD/SMT
• Package / Case: VQFN-48
• Snr: 100 dB

STA381BWS
7.19
Two different behaviors can be configured by the VRESTG bit.
If VRESTG=’0’ the CxVR contribution will be applied immediately after the corresponding
I
If VRESTG=’1’ the CxVR bits will be effective on channel volume only after the
corresponding CxVol register or master volume register is written (even to the previous
values).
Table 163. Extra volume resolution enable
PLL configuration registers (address 0x41; 0x42; 0x43; 0x44;
0x45; 0X46)
By default the STA381BWS is able to configure the embedded PLL automatically depending
on the MCS bits (reg 0x00). For certain applications and to provide flexibility to the user, a
manual PLL configuration can be used (setting PLL_DIRP to ‘1’).
2
C bits are written.
PLL_DPD
Reserved
Reserved
NA
D7
D7
D7
D7
D7
D7
VRESEN
0
0
0
0
0
PLL_DITH[1:0]
0
0
1
1
PLL_FCT
Reserved
Reserved
NA
D6
D6
D6
D6
D6
D6
0
0
0
0
0
VRESTG
PLL_DIRP
PLL_STB
Reserved
0
1
0
1
NA
D5
D5
D5
D5
D5
D5
0
0
0
0
0
Doc ID 018937 Rev 6
PLL_STBBYP
Extra volume resolution disabled
Extra volume resolution disabled
Fine volume tuning enabled and applied immediately
Fine volume tuning enabled and applied when master or
channel volume is updated
PLL_PWD
Register description: Sound Terminal compatibility
Reserved
NA
D4
D4
D4
D4
D4
D4
0
0
0
0
0
PLL_FRAC[15:8]
PLL_FRAC[7:0]
BYPSTATE
PLL_BYP
NA
D3
D3
D3
D3
D3
D3
0
0
0
0
0
PLL_NDIV[5:0]
PDSTATE
OSC_PD
Mode
D2
D2
D2
D2
D2
D2
NA
0
0
0
0
1
PLL_IDIV(3:0)
Reserved
OSCOK
NA
D1
D1
D1
D1
D1
D1
0
0
0
0
0
BOOST32K
LOWCK
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NA
D0
D0
D0
D0
D0
D0
0
0
0
0
0