STA381BWSTR STMicroelectronics, STA381BWSTR Datasheet - Page 151

• Manufacturer Part Number: STA381BWSTR
• Description: Audio DSPs Sound Terminal 2.1 High EFF Dig Audio
• Manufacturer: STMicroelectronics

Specifications of STA381BWSTR

• Product Category: Audio DSPs
• Rohs: yes
• Operating Supply Voltage: 4.5 V to 25.5 V
• Operating Temperature Range: 0 C to + 150 C
• Mounting Style: SMD/SMT
• Package / Case: VQFN-48
• Snr: 100 dB

STA381BWS
7.21
7.22
7.22.1
Extended coefficient range up to -4...4 (address 0x49, 0x4A)
Biquads from 1 to 7 have in the STA381BWS the possibility to extend the coefficient range
from [-1,1) to [-4..4) which allows the implementation of high-shelf filters that may require a
coefficient dynamic greater in absolute value than 1.
Three ranges are available, [-1;1) [-2;2) [-4;4). By default, the extended range is activated
Each biquad has its independent setting according to the following table.
Table 169. Coefficients extended range configuration
In this case the user can decide, for each filter stage, the right coefficients range. Note that
for a given biquad, the same range will be applied to the left and right (channel 1 and
channel 2).
Crossover biquad does not have the availability of this feature, maintaining the [-1;1) range
unchanged.
Miscellaneous registers (address 0x4B, 0x4C)
Rate power-down enable (RPDNEN) bit (address 0x4B, bit D7)
In the STA381BWS, by default, the power-down pin and I
commands to perform the fade-out. This default can be changed so that the fade-out can be
started using master volume. The RPDNEN bit, when set, activates this feature.
CEXT_B4[1]
RPDNEN
reserved
LPDP
D7
D7
D7
D7
1
0
0
0
CEXT_Bx[1]
CEXT_B4[0]
reserved
0
0
1
1
LPD
D6
D6
D6
D6
0
0
1
1
CEXT_B3[1]
CEXT_B7[1]
BRIDGOFF
LPDE
D5
D5
D5
D5
1
1
1
0
Doc ID 018937 Rev 6
CEXT_B3[0]
CEXT_B7[0]
PNDLSL[2]
Register description: Sound Terminal compatibility
D4
D4
D4
D4
0
0
0
0
CEXT_Bx[0]
0
1
0
1
CEXT_B2[1]
CEXT_B6[1]
PNDLSL[1]
D3
D3
D3
D3
1
1
0
1
2
C power-down act on mute
CEXT_B2[0]
CEXT_B6[0]
PNDLSL[0]
CPWMEN
D2
D2
D2
D2
0
0
1
1
CEXT_B1[1]
CEXT_B51]
reserved
reserved
Reserved
D1
D1
D1
D1
1
1
0
0
Range
[-1;1)
[-2;2)
[-4;4)
CEXT_B1[0]
CEXT_B5[0]
SHEN
151/171
D0
D0
D0
D0
0
0
0
0