MA240017 Microchip Technology, MA240017 Datasheet - Page 69

• Manufacturer Part Number: MA240017
• Description: MODULE PLUG-IN PIC24F16KA102 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA240017

• Accessory Type: Plug-In Module (PIM) - PIC24F16KA102
• Product: Microcontroller Modules
• Data Bus Width: 16 bit
• Core Processor: PIC24F16KA102
• Operating Supply Voltage: 3 V to 3.6 V
• Development Tools By Supplier: Integrated Development Environment, Assembler, ANSI C Compiler
• Processor Series: PIC24F
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC24
• Silicon Core Number: PIC24F
• Silicon Family Name: PIC24FxxKAxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Explorer 16 (DM240001 or DM240002)
• For Use With: DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 8-1:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-9
bit 7-5
Note 1:
R/W-0, HSC R/W-0, HSC R/W-0, HSC
Note:
IPL2
U-0
—
2:
3:
(2,3)
See Register 3-1 for the description of these bits, which are not dedicated to interrupt control functions.
The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level.
The value in parentheses indicates the interrupt priority level if IPL3 = 1.
The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
Bit 8 and bits 4 through 0 are described in Section 3.0 “CPU”.
Unimplemented: Read as ‘0’
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU interrupt priority level is 7 (15); user interrupts disabled
110 = CPU interrupt priority level is 6 (14)
101 = CPU interrupt priority level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
IPL1
U-0
—
(2,3)
SR: ALU STATUS REGISTER
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
IPL0
U-0
—
(2,3)
R-0, HSC
RA
U-0
—
Preliminary
(1)
PIC24F16KA102 FAMILY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC
U-0
N
(2,3)
—
(1)
OV
U-0
—
(1)
x = Bit is unknown
U-0
Z
—
(1)
DS39927B-page 67
R-0, HSC
DC
C
(1)
(1)
bit 8
bit 0