AT89C51CC03C-S3RIM Atmel, AT89C51CC03C-S3RIM Datasheet - Page 130

• Manufacturer Part Number: AT89C51CC03C-S3RIM
• Description: IC 8051 MCU FLASH 64K 52PLCC
• Manufacturer: Atmel
• Series: AT89C CANr

Specifications of AT89C51CC03C-S3RIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT89C51CC03CS3RTR

Baud Rate
130
AT89C51CC03
In a Master configuration, the SS line can be used in conjunction with the MODF flag in
the SPI Status register (SPSCR) to prevent multiple masters from driving MOSI and
SCK (see Error conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
•
•
Note:
In Master mode, the baud rate can be selected from a baud rate generator which is con-
trolled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is
selected from one of seven clock rates resulting from the division of the internal clock by
4, 8, 16, 32, 64 or 128.
Table 90 gives the different clock rates selected by SPR2:SPR1:SPR0.
In Slave mode, the maximum baud rate allowed on the SCK input is limited to F
Table 90. SPI Master Baud Rate Selection
SPR2
The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the network
and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in
the SPSCR will never be set
The Device is configured as a Slave with CPHA and SSDIS control bits set
kind of configuration can happen when the system includes one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the SS pin to select the communicating Slave device.
0
0
0
0
1
1
1
1
1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA =’0’ because in
this mode, the SS is used to start the transmission.
SPR1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
(1)
.
F
F
F
F
F
CLK PERIPH
Clock Rate
F
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
Don’t Use
Don’t Use
CLK PERIPH
/128
/16
/32
/64
/8
/4
Baud Rate Divisor (BD)
4182O–CAN–09/08
No BRG
No BRG
128
16
32
64
4
8
(2)
sys
. This
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