AT89C51CC03C-S3RIM Atmel, AT89C51CC03C-S3RIM Datasheet - Page 139

IC 8051 MCU FLASH 64K 52PLCC

AT89C51CC03C-S3RIM

Manufacturer Part Number
AT89C51CC03C-S3RIM
Description
IC 8051 MCU FLASH 64K 52PLCC
Manufacturer
Atmel
Series
AT89C CANr

Specifications of AT89C51CC03C-S3RIM

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT89C51CC03CS3RTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51CC03C-S3RIM
Manufacturer:
Atmel
Quantity:
10 000
Serial Peripheral DATa Register
(SPDAT)
4182O–CAN–09/08
Reset Value = 00X0 XXXXb
Not Bit addressable
The Serial Peripheral Data Register (Table 94) is a read/write buffer for the receive data
register. A write to SPDAT places data directly into the shift register. No transmit buffer is
available in this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content
of the shift register.
Table 94. SPDAT Register
SPDAT - Serial Peripheral Data Register (0D6H)
Reset Value = Indeterminate
R7:R0: Receive data bits
Number
Bit
R7
7
4
3
2
1
0
Mnemonic Description
MODFIE
UARTM
SPTEIE
MODF
SPTE
Bit
R6
6
Mode Fault
- Set by hardware to indicate that the SS pin is in inappropriate logic level (in both
master and slave modes).
- Cleared by hardware when reading SPSCR
When MODF error occurred:
- In slave mode: SPI interface ignores all transmitted data while SS remains high.
A new transmission is perform as soon as SS returns low.
- In master mode: SPI interface is disabled (SPEN=0, see description for SPEN
bit in SPCON register).
Serial Peripheral Transmit register Empty
- Set by hardware when transmit register is empty (if needed, SPDAT can be
loaded with another data).
- Cleared by hardware when transmit register is full (no more data should be
loaded in SPDAT).
Serial Peripheral UART mode
Set and cleared by software:
- Clear: Normal mode, data are transmitted MSB first (default)
- Set: UART mode, data are transmitted LSB first.
Interrupt Enable for SPTE
Set and cleared by software:
- Set to enable SPTE interrupt generation (when SPTE goes high, an interrupt is
generated).
- Clear to disable SPTE interrupt generation
Caution: When SPTEIE is set no interrupt generation occurred when SPIF flag
goes high. To enable SPIF interrupt again, SPTEIE should be cleared.
Interrupt Enable for MODF
Set and cleared by software:
- Set to enable MODF interrupt generation
- Clear to disable MODF interrupt generation
R5
5
R4
4
R3
3
R2
AT89C51CC03
2
R1
1
R0
0
139

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