AT89C51CC03C-S3RIM Atmel, AT89C51CC03C-S3RIM Datasheet - Page 63

• Manufacturer Part Number: AT89C51CC03C-S3RIM
• Description: IC 8051 MCU FLASH 64K 52PLCC
• Manufacturer: Atmel
• Series: AT89C CANr

Specifications of AT89C51CC03C-S3RIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT89C51CC03CS3RTR

Automatic Address
Recognition
4182O–CAN–09/08
valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the
stop bit instead of the last data bit (See Figure 33. and Figure 34.).
Figure 33. UART Timing in Mode 1
Figure 34. UART Timing in Modes 2 and 3
The automatic address recognition feature is enabled when the multiprocessor commu-
nication feature is enabled (SM2 bit in SCON register is set).
Implemented in the hardware, automatic address recognition enhances the multiproces-
sor communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address will the
receiver set the RI bit in the SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If necessary, you can enable the automatic address recognition feature in mode 1. In
this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when
the received command frame address matches the device’s address and is terminated
by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
SMOD0=0
SMOD0=1
SMOD0=1
SMOD0=X
SMOD0=1
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
RXD
RXD
FE
RI
RI
FE
RI
Start
Start
bit
bit
D0
D0
D1
D1
D2
D2
D3
D3
Data byte
Data byte
D4
D4
D5
D5
D6
D6
AT89C51CC03
D7
D7
Ninth
Stop
D8
bit
bit
Stop
bit
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