PIC32MX440F512H-80I/MR Microchip Technology, PIC32MX440F512H-80I/MR Datasheet - Page 21

• Manufacturer Part Number: PIC32MX440F512H-80I/MR
• Description: IC PIC MCU FLASH 512KX32 64-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/MR

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Controller Family/series: PIC32
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI, USB
• No. Of Pwm Channels: 5
• Embedded Interface Type: EUSART, I2C, SPI, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, SPI, TWI, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.0
The MCU module is the heart of the PIC32MX3XX/4XX
Family processor. The MCU fetches instructions,
decodes each instruction, fetches source operands,
executes each instruction, and writes the results of
instruction execution to the proper destinations.
3.1
• 5-stage pipeline
• 32-bit Address and Data Paths
• MIPS32 Enhanced Architecture (Release 2)
FIGURE 3-1:
© 2009 Microchip Technology Inc.
Note:
- Multiply-Accumulate and Multiply-Subtract
- Targeted Multiply Instruction
- Zero/One Detect Instructions
- WAIT Instruction
- Conditional Move Instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
- Bit field manipulation instructions
Instructions
for interrupt handlers
PIC32MX MCU
Features
reference source. Refer to the “PIC32MX
available from the Microchip web site
This data sheet summarizes the features of
the PIC32MX3XX/4XX Family of devices. It
is not intended to be a comprehensive
Family Reference Manual” Section 2.
“MCU” (DS61113) for a detailed description
of the PIC32MX MCU. The manual is
(www.Microchip.com/PIC32). Resources for
the MIPS32
available
ucts/cores/32-bit-cores/ mips32-m4k/#.
MCU BLOCK DIAGRAM
(RF/ALU/Shift)
Coprocessor
®
Execution
System
at
M4K
MDU
Core
®
Processor Core are
www.mips.com/prod-
FMT
Preliminary
Bus Interface
• MIPS16e™ Code Compression
• Simple Fixed Mapping Translation (FMT)
• Simple Dual Bus Interface
• Autonomous Multiply/Divide Unit
• Power Control
• EJTAG Debug and Instruction Trace
- 16-bit encoding of 32-bit instructions to
- Special PC-relative instructions for efficient
- SAVE & RESTORE macro instructions for
- Improved support for handling 8 and 16-bit
mechanism
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
- Maximum issue rate of one 32x16 multiply
- Maximum issue rate of one 32x32 multiply
- Early-in iterative divide. Minimum 11 and
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
- Extensive use of local gated clocks
- Support for single stepping
- Virtual instruction and data address/value
- breakpoints
- PC tracing with trace compression
EJTAG
improve code density
loading of addresses and constants
setting up and tearing down stack frames
within subroutines
data types
interrupt latency
per clock
every other clock
maximum 34 clock latency (dividend (rs) sign
extension-dependent)
instruction)
Power
Mgmt
Trace
TAP
PIC32MX3XX/4XX
Dual Bus I/F
Debug I/F
Off-Chip
Trace I/F
DS61143F-page 19