PIC32MX440F512H-80I/MR Microchip Technology, PIC32MX440F512H-80I/MR Datasheet - Page 48

• Manufacturer Part Number: PIC32MX440F512H-80I/MR
• Description: IC PIC MCU FLASH 512KX32 64-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/MR

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Controller Family/series: PIC32
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI, USB
• No. Of Pwm Channels: 5
• Embedded Interface Type: EUSART, I2C, SPI, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, SPI, TWI, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 4-16:
TABLE 4-17:
Legend:
Note
Legend:
Note
BF80_F000 OSCCON
BF80_F010
BF80_0000 WDTCON
BF80_F600
BF80_F610 RSWRST
BF88_6000 TRISA
BF88_6010 PORTA
BF88_6020 LATA
BF88_6030 ODCA
BF88_6040 TRISB
BF88_6050 PORTB
Virtual
Virtual
Addr
Addr
SFR
SFR
1:
1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
11:
OSCTUN
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-
mation.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as ‘0’.
JTAG program/debug port is multiplexed with port pins RA0, RA1, RA4 and RA5 on 100-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.
On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain
these pins as general purpose I/O pins, the user’s application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction TRACE pins, TROEN must be set = 1.
JTAG program/debug port is multiplexed with port pins RB10, RB11, RB12 and RB13 on 64-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.
Port Pin RB3 is not available as a general purpose I/O pin when the USB module is enabled.
Not implemented on 64-pin devices. Read as ‘0’.
Not implemented on 64-pin USB devices. Read as ‘0’.
Not implemented on 100-pin USB devices. Read as ‘0’.
Not available as a general purpose I/O pin when USB module is enabled.
Not available as a general purpose I/O pin when USB module is enabled. Input only when the USB module is disabled.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-
mation.
Name
RCON
Name
SFR
SFR
(1,2,3)
(1,2,3)
(1,2,3)
(1,2,3)
(4,5)
(4,5)
SYSTEM CONTROL REGISTERS MAP
PORT A-G REGISTERS MAP
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
TRISA15
ODCA15
LATA15
31/15
31/15
RA15
Bits
Bits
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISA14
ODCA14
LATA14
30/14
30/14
RA14
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
COSC<2:0>
29/13
29/13
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PLLODIV<2:0>
(11)
28/12
28/12
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
27/11
27/11
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
TRISA10
ODCA10
LATA10
26/10
26/10
RA10
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RCDIV<2:0>
NOSC<2:0>
TRISA9
ODCA9
LATA9
25/9
Bits
25/9
Bits
RA9
CM
—
—
—
—
—
—
—
—
—
—
—
—
—
VREGS
Bits
24/8
Bits
24/8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISB<15:0>
RB<15:0>
CLKLOCK
EXTR
23/7
Bits
23/7
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SOSCRDY
ULOCK
SWR
22/6
Bits
22/6
Bits
—
—
—
—
—
—
—
—
—
—
—
—
LOCK
21/5
Bits
21/5
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
SWDTPS<4:0>
SLPEN
WDTO
20/4
20/4
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
PBDIV<1:0>
TRISA<7:0>
ODCA<7:0>
LATA<7:0>
RA<7:0>
SLEEP
19/3
Bits
19/3
Bits
CF
—
—
—
—
—
—
—
—
—
—
—
TUN<5:0>
UFRCEN
IDLE
18/2
Bits
18/2
Bits
—
—
—
—
—
—
—
—
—
—
—
PLLMULT<2:0>
SOSCEN
Bits
17/1
Bits
17/1
BOR
—
—
—
—
—
—
—
—
—
—
—
—
WDTCLR
OSWEN
SWRST
POR
Bits
16/0
Bits
16/0
—
—
—
—
—
—
—
—
—
—