PIC32MX440F512H-80I/MR Microchip Technology, PIC32MX440F512H-80I/MR Datasheet - Page 52

IC PIC MCU FLASH 512KX32 64-QFN

PIC32MX440F512H-80I/MR

Manufacturer Part Number
PIC32MX440F512H-80I/MR
Description
IC PIC MCU FLASH 512KX32 64-QFN
Manufacturer
Microchip Technology
Series
PIC® 32MXr

Specifications of PIC32MX440F512H-80I/MR

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI, USB
No. Of Pwm Channels
5
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, JTAG, SPI, TWI, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
51
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
TABLE 4-21:
TABLE 4-22:
BF88_40C0 CHEPFABT
Legend:
Note
Legend:
Note
BF88_4000 CHECON
BF88_4010 CHEACC
BF88_4020 CHETAG
BF88_4030 CHEMSK
BF88_4040
BF88_4050
BF88_4060
BF88_4070
BF88_4080
BF88_4090
BF88_40A0
BF80_0200
BF80_0210 RTCALRM
Virtual
Virtual
Addr
Addr
SFR
SFR
1:
1:
CHELRU
RTCCON
CHEMIS
CHEHIT
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
CHEW0
CHEW1
CHEW2
CHEW3
Name
Name
SFR
SFR
(1)
(1)
(1)
(1)
PREFETCH REGISTERS MAP
RTCC REGISTERS MAP
31:16
31:16 CHEWEN
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
ALRMEN
31/15
BOOT
31/15
LTAG
Bits
Bits
ON
CHIME
30/14
30/14
Bits
Bits
FRZ
29/13
29/13
SIDL
Bits
Bits
PIV
(1)
28/12
28/12
ALRM
SYNC
Bits
Bits
27/11
27/11
Bits
Bits
LMASK<15:5>
26/10
26/10
Bits
Bits
AMASK<3:0>
LTAG<15:4>
Bits
25/9
Bits
25/9
DCSZ<1:0>
CHEPFABT<31:0>
Bits
24/8
CHELRU<15:0>
Bits
24/8
CHEMIS<31:0>
CHEW0<31:0>
CHEW1<31:0>
CHEW2<31:0>
CHEW3<31:0>
CHEHIT<31:0>
RTSEC
23/7
23/7
Bits
Bits
SEL
CLKON
Bits
22/6
Bits
22/6
RTC
Bits
21/5
Bits
21/5
PREFEN<1:0>
CAL<11:0>
CHELRU<24:16>
20/4
20/4
Bits
Bits
LTAG<23:16>
ARPT<7:0>
RTCWREN RTCSYNC HALFSEC
LVALID
Bits
19/3
Bits
19/3
LLOCK
Bits
18/2
Bits
18/2
CHEIDX<3:0>
PFMWS<2:0>
LTYPE
17/1
17/1
Bits
Bits
CHECOH
RTCOE
16/0
16/0
Bits
Bits

Related parts for PIC32MX440F512H-80I/MR