PIC32MX440F512H-80I/MR Microchip Technology, PIC32MX440F512H-80I/MR Datasheet - Page 27

IC PIC MCU FLASH 512KX32 64-QFN

PIC32MX440F512H-80I/MR

Manufacturer Part Number
PIC32MX440F512H-80I/MR
Description
IC PIC MCU FLASH 512KX32 64-QFN
Manufacturer
Microchip Technology
Series
PIC® 32MXr

Specifications of PIC32MX440F512H-80I/MR

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI, USB
No. Of Pwm Channels
5
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, JTAG, SPI, TWI, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
51
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
4.0
PIC32MX3XX/4XX microcontrollers provide 4 GB of
unified virtual memory address space. All memory
regions including program, data memory, SFRs, and
Configuration registers reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX3XX/4XX to
execute from data memory.
Key Features:
• 32-bit native data width
• Separate User and Kernel mode address space
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
• Simple memory mapping with Fixed Mapping
• Cacheable and non-cacheable address regions
© 2009 Microchip Technology Inc.
Note:
program space
runaway code.
Translation (FMT) unit
MEMORY ORGANIZATION
reference source. Refer to the “PIC32MX
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
Family Reference Manual” Section 3.
“Memory Organization” (DS61115) for a
detailed description of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
Preliminary
4.1
PIC32MX3XX/4XX microcontrollers implement two
address spaces: Virtual and Physical. All hardware
resources such as program memory, data memory, and
peripherals are located at their respective physical
addresses. Virtual addresses are exclusively used by
the CPU to fetch and execute instructions as well as
access peripherals. Physical addresses are used by
peripherals such as DMA and Flash controller that
access memory independently of CPU.
PIC32MX3XX/4XX
PIC32MX3XX/4XX Memory Layout
DS61143F-page 25

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