LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 173

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
UM10375
User manual
11.6.8 UART Modem Control Register
Table 195. UART Line Control Register (U0LCR - address 0x4000 800C) bit description
The U0MCR enables the modem loopback mode and controls the modem output signals.
Table 196. UART0 Modem Control Register (U0MCR - address 0x4000 8010) bit description
Bit
2
3
5:4
6
7
31:
8
Bit
0
1
3-2
Symbol Value Description
Stop Bit
Select
Parity
Enable
Parity
Select
Break
Control
Divisor
Latch
Access
Bit
(DLAB)
-
Symbol
DTR
Control
RTS
Control
-
0
1
0
1
00
01
10
11
0
1
0
1
-
All information provided in this document is subject to legal disclaimers.
Value Description
NA
1 stop bit.
2 stop bits (1.5 if U0LCR[1:0]=00).
Disable parity generation and checking.
Enable parity generation and checking.
Odd parity. Number of 1s in the transmitted character and the
attached parity bit will be odd.
Even Parity. Number of 1s in the transmitted character and the
attached parity bit will be even.
Forced "1" stick parity.
Forced "0" stick parity.
Disable break transmission.
Enable break transmission. Output pin UART TXD is forced to logic
0 when U0LCR[6] is active high.
Disable access to Divisor Latches.
Enable access to Divisor Latches.
Reserved
Source for modem output pin, DTR. This bit reads as 0 when
modem loopback mode is active.
Source for modem output pin RTS. This bit reads as 0 when
modem loopback mode is active.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 2 — 7 July 2010
Chapter 11: LPC13xx UART
UM10375
© NXP B.V. 2010. All rights reserved.
175 of 333
Reset
Value
0
0
0
0
0
-
Reset
value
0
0
0