LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 58

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
UM10375
User manual
5.6.3 Interrupt Clear-Enable Register 0
Table 64.
The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the
enabled state of those interrupts. The remaining interrupts are disabled via the ICER1
register
registers
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 disables the interrupt.
Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Table 65.
Bit
11
12
13
14
15
16
17
18
19
20
21
22
23
24
31:25 -
Bit
0
1
2
3
4
5
6
7
8
9
10
11
Name
ICE_PIO0_0
ICE_PIO0_1
ICE_PIO0_2
ICE_PIO0_3
ICE_PIO0_4
ICE_PIO0_5
ICE_PIO0_6
ICE_PIO0_7
ICE_PIO0_8
ICE_PIO0_9
ICE_PIO0_10
ICE_PIO0_11
Name
ISE_CT32B0
ISE_CT32B1
ISE_SSP
ISE_UART
ISE_USBIRQ
ISE_USBFRQ
ISE_ADC
ISE_WDT
ISE_BOD
-
ISE_PIO_3
ISE_PIO_2
ISE_PIO_1
ISE_PIO_0
(Section
(Section 5.6.1
Interrupt Set-Enable Register 1 register (ISER1 - address 0xE000 E104) bit
description
Interrupt Clear-Enable Register 0
All information provided in this document is subject to legal disclaimers.
5.6.4). Enabling interrupts is done through the ISER0 and ISER1
Description
PIO0_0 start logic input interrupt disable.
PIO0_1 start logic input interrupt disable.
PIO0_2 start logic input interrupt disable.
PIO0_3 start logic input interrupt disable.
PIO0_4 start logic input interrupt disable.
PIO0_5 start logic input interrupt disable.
PIO0_6 start logic input interrupt disable.
PIO0_7 start logic input interrupt disable.
PIO0_8 start logic input interrupt disable.
PIO0_9 start logic input interrupt disable.
PIO0_10 start logic input interrupt disable.
PIO0_11 start logic input interrupt disable.
…continued
Timer CT32B0 interrupt enable.
Timer CT32B1 interrupt enable.
UART interrupt enable.
USB IRQ interrupt enable.
ADC interrupt enable.
WDT interrupt enable.
Description
SSP interrupt enable.
USB FRQ interrupt enable.
BOD interrupt enable.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
GPIO port 3 interrupt enable.
GPIO port 2 interrupt enable.
GPIO port 1 interrupt enable.
GPIO port 0 interrupt enable.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
and
Rev. 2 — 7 July 2010
Section
5.6.2).
Chapter 5: LPC13xx Interrupt controller
UM10375
© NXP B.V. 2010. All rights reserved.
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