LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 28

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
UM10375
User manual
3.5.27 WDT clock source update enable register
3.5.28 WDT clock divider register
3.5.29 CLKOUT clock source select register
Table 31.
This register updates the clock source of the watchdog timer with the new input clock after
the WDTCLKSEL register has been written to. In order for the update to take effect at the
input of the watchdog timer, first write a zero to the WDTCLKUEN register and then write
a one to WDTCLKUEN.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Table 32.
This register determines the divider values for the watchdog clock wdt_clk.
Table 33.
This register configures the clkout_clk signal to be output on the CLKOUT pin. All three
oscillators and the main clock can be selected for the clkout_clk clock.
The CLKOUTCLKUEN register (see
for the update to take effect.
Bit
1:0
31:2
Bit
0
31:1
Bit
7:0
31:8
Symbol
SEL
-
Symbol
ENA
-
Symbol
DIV
-
WDT clock source select register (WDTCLKSEL, address 0x4004 80D0) bit
description
WDT clock source update enable register (WDTCLKUEN, address 0x4004 80D4)
bit description
WDT clock divider register (WDTCLKDIV, address 0x4004 80D8) bit description
All information provided in this document is subject to legal disclaimers.
Value
00
01
10
11
Value
0
1
to
255
-
-
Value
0
1
-
Rev. 2 — 7 July 2010
Description
WDT clock source
IRC oscillator
Main clock
Watchdog oscillator
Reserved
Reserved
Description
WDT clock divider values
Disable
Divide by 1
...
Divide by 255
Reserved
Description
Enable WDT clock source update
No change
Update clock source
Reserved
Section
Chapter 3: LPC13xx System configuration
3.5.30) must be toggled from LOW to HIGH
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0x0
0x00
29 of 333
Reset
value
0x00
0x00
Reset
value
0x00
0x00