LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 52
LPC1342FHN33,551
Manufacturer Part Number
LPC1342FHN33,551
Description
IC MCU 32BIT 16KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1342FHN33,551
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
4 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4946
935289656551
935289656551
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5.1 How to read this chapter
5.2 Introduction
5.3 Features
5.4 Interrupt sources
UM10375
User manual
Interrupts 47 and 48 in
interrupts are reserved on parts LPC1311/13.
The implementation of start logic wake-up interrupts depends on how many PIO port pins
are available (see
interrupt 38 are available.
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
Refer to the Cortex-M3 Technical Reference Manual for details of NVIC operation.
Table 61
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. There is no significance or priority about what
line is connected where except for certain standards from ARM.
•
•
•
•
•
•
•
UM10375
Chapter 5: LPC13xx Interrupt controller
Rev. 2 — 7 July 2010
Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3.
Tightly coupled interrupt controller provides low interrupt latency.
Controls system exceptions and peripheral interrupts.
In the LPC13xx, the NVIC supports up to 56 vectored interrupts.
8 programmable interrupt priority levels with hardware priority level masking.
Relocatable vector table.
Software interrupt generation.
lists the interrupt sources for each peripheral function. Each peripheral device
All information provided in this document is subject to legal disclaimers.
Section
Table 61
Rev. 2 — 7 July 2010
3.1). For HVQFN packages only wake-up interrupts 0 to 24 and
are available on parts LPC1342/43 with USB only. These
© NXP B.V. 2010. All rights reserved.
User manual
53 of 333
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