LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 289

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
19.3 Features
19.4 Description
UM10375
User manual
The bootloader code is executed every time the part is powered on or reset (see
Figure
application code, or it can obtain the boot image as an attached MSC device through
USB. A LOW level during reset at the PIO0_1 pin is considered an external hardware
request to start the ISP command handler or the USB device enumeration without
checking for a valid user code first. The state of PIO0_3 determines whether the UART or
USB interface will be used:
Remark: On the LPC131x parts (no USB), the state of pin PIO0_3 does not matter.
Assuming that power supply pins are at their nominal levels when the rising edge on
RESET pin is generated, it may take up to 3 ms before PIO0_1 is sampled and the
decision whether to continue with user code or ISP handler/USB is made. If PIO0_1 is
sampled low and the watchdog overflow flag is set, the external hardware request to start
the ISP command handler is ignored. If there is no request for the ISP command handler
1. In the user code, the memory location must be initialized as follows to create a
2. If the USB ISP mode is entered on power-up (see
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work-around for this issue:
*((unit32_t *)(0x1000 0054)) = 0x0;
initialized, and no user code is executed which could write to this memory location.
Therefore the device times out when first connected to the Windows operating
system, and the MSD disk only appears after a time-out and retry, which takes 45 sec
or longer. A work-around for the time-out issue is not available.
In-System Programming: In-System programming (ISP) is programming or
reprogramming the on-chip flash memory, using the bootloader software and UART
serial port or the USB interface. This can be done when the part resides in the
end-user board.
In Application Programming: In-Application (IAP) programming is performing erase
and write operation on the on-chip flash memory, as directed by the end-user
application code.
The LPC134x supports ISP from the USB port through enumeration as a Mass
Storage Class (MSC) Device when connected to a USB host interface (Windows
operating system only).
Flash access times can be configured through a register in the flash controller block.
Erase time for one sector is 100 ms ± 5%. Programming time for one block of
256 bytes is 1 ms ± 5%.
If PIO0_3 is sampled HIGH, the bootloader connects the LPC134x as a MSC USB
device to a PC host. The LPC134x flash memory space is represented as a drive in
the host’s Windows operating system.
If PIO0_3 is sampled LOW, the bootloader configures the UART serial port and calls
the ISP command handler.
55). The loader can either execute the ISP command handler or the user
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 19: LPC13xx Flash memory programming firmware
Section
19.3), the memory is not
UM10375
© NXP B.V. 2010. All rights reserved.
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