LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 279

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
UM10375
User manual
17.7.1 Watchdog Mode register (WDMOD - 0x4000 0000)
Table 271. Register overview: Watchdog timer (base address 0x4000 4000)
[1]
The WDMOD register controls the operation of the Watchdog through the combination of
WDEN and RESET bits. Note that a watchdog feed must be performed before any
changes to the WDMOD register take effect.
Table 272. Watchdog Mode register (WDMOD - address 0x4000 4000) bit description
Once the WDEN and/or WDRESET bits are set they can not be cleared by software. Both
flags are cleared by reset or a Watchdog timer underflow.
WDTOF The Watchdog time-out flag is set when the Watchdog times out. This flag is
cleared by software or any reset except the WDT reset.
WDINT The Watchdog interrupt flag is set when the Watchdog times out. This flag is
cleared when any reset occurs. Once the watchdog interrupt is serviced, it can be
disabled in the NVIC or the watchdog interrupt request will be generated indefinitely. the
intent of the watchdog interrupt is to allow debugging watchdog activity without resetting
the device when the watchdog overflows.
Watchdog reset or interrupt will occur any time the watchdog is running and has an
operating clock source. Any clock source works in Sleep mode, and if a watchdog
interrupt occurs in Sleep mode, it will wake up the device.
Name
WDMOD
WDTC
WDFEED
WDTV
Bit
0
1
2
3
7:4
31:8 -
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Symbol
WDEN
WDRESET WDRESET Watchdog reset enable bit (Set Only). When 1,
WDTOF
WDINT
-
Access Address
R/W
R/W
WO
RO
All information provided in this document is subject to legal disclaimers.
Description
WDEN Watchdog enable bit (Set Only). When 1, the
watchdog timer is running.
a watchdog time-out will cause a chip reset.
WDTOF Watchdog time-out flag. Set when the watchdog
timer times out, cleared by software.
WDINT Watchdog interrupt flag (Read Only, not clearable
by software).
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
reserved
offset
0x000
0x004
0x008
0x00C
Rev. 2 — 7 July 2010
Description
Watchdog mode register. This register contains the
basic mode and status of the Watchdog Timer.
Watchdog timer constant register. This register
determines the time-out value.
Watchdog feed sequence register. Writing 0xAA
followed by 0x55 to this register reloads the
Watchdog timer with the value contained in WDTC.
Watchdog timer value register. This register reads
out the current value of the Watchdog timer.
Chapter 17: LPC13xx WatchDog Timer (WDT)
UM10375
© NXP B.V. 2010. All rights reserved.
Reset Value
0
0
0 (After any
reset except
WDT)
0
NA
-
281 of 333
Reset
Value
0
0xFF
NA
0xFF
[1]