P87C591VFA/00,512 NXP Semiconductors, P87C591VFA/00,512 Datasheet - Page 10

• Manufacturer Part Number: P87C591VFA/00,512
• Description: IC 80C51 MCU 16K OTP 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C591VFA/00,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: CAN, EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN, I2C, UART
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1256-5; 935268182512; P87C591VFAA

Philips Semiconductors
2000 Jul 26
P2.0/A08 to
P2.7/A15
PSEN
ALE/PROG
EA/V
P0.0/AD0 to
P0.7/AD7
AV
AV
Single-chip 8-bit microcontroller with CAN controller
ref+
SS
SYMBOL
PP
18 to 25 24 to 31 Port 2 (P2.0 to P2.7): 8-bit programmable I/O port lines;
26
27
29
30 to 37 36 to 43 Port 0: 8-bit open-drain bidirectional I/O port.
38
39
QFP44 PLCC44
PIN
32
33
35
44
1
A08 to A15: High-order address byte for external memory.
Alternate function: High-order address byte for external memory (A08-A15).
Port 2 is also used to input the upper order address during EPROM
programming and verification. A8 is on P2.0, A9 on P2.1, through A12 on
P2.4.
During reset, Port 2 will be asynchronously driven HIGH.
Port 2 has four output modes selected on a per bit basis by writing to the
P2M1 and P2M2 registers as follows:
P2M1.x
Program Store Enable output: read strobe to the external Program Memory
via Ports 0 and 2. Is activated twice each machine cycle during fetches from
external Program Memory. When executing out of external Program Memory
two activations of PSEN are skipped during each access to external Data
Memory. PSEN is not activated (remains HIGH) during no fetches from
external Program Memory. PSEN can sink/source 8 LSTTL inputs. It can
drive CMOS inputs without external pull-ups.
Address Latch Enable output. Latches the low byte of the address during
access of external memory in normal operation. It is activated every six
oscillator periods except during an external Data Memory access. ALE can
sink/source 8 LSTTL inputs. It can drive CMOS inputs without an external
pull-up. To prohibit the toggling of ALE pin (RFI noise reduction) the bit A0
(SFR: AUXR.0) must be set by software; see Table 4.
PROG: the programming pulse input; alternative function for the P87C591.
External Access input. If, during reset, EA is held at a TTL level HIGH the
CPU executes out of the internal Program Memory. If, during reset, EA is held
at a TTL level LOW the CPU executes out of external Program Memory via
Port 0 and Port 2. EA is not allowed to float. EA is latched during reset and
don’t care after reset.
V
During reset, Port 0 is HIGH-Impedance (Tri-State).
AD7 to AD0: Multiplexed Low-order address and Data bus for external
memory. During these accesses internal pull-ups are activated. Port 0 can
sink/source up to 8 LSTTL inputs.
Analog to Digital Conversion Reference Resistor: High-end.
Analog ground.
PP
0
0
1
1
: the programming supply voltage; alternative function for the P87C591.
P2M2.x
0
1
0
1
10
Mode Description
Pseudo-bidirectional (standard c51 configuration default)
Push-Pull
High impedance
Open drain
DESCRIPTION
Preliminary Specification
P8xC591