P87C591VFA/00,512 NXP Semiconductors, P87C591VFA/00,512 Datasheet - Page 144

• Manufacturer Part Number: P87C591VFA/00,512
• Description: IC 80C51 MCU 16K OTP 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C591VFA/00,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: CAN, EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN, I2C, UART
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1256-5; 935268182512; P87C591VFAA

Philips Semiconductors
Notes to the DC characteristics
1. 8-bit mode
2. See Figures 62 through 64 for I
3. The operating supply current is measured with all output pins disconnected; XTAL1 driven with
4. The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
5. The Power-down current is measured with all output pins disconnected; XTAL2 not connected;
6. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
7. Pins of Port 1 (except P1.6, P1.7), 2 and 3 source a transition current when they are being externally driven from
8. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the V
9. Capacitive loading on Ports 0 and 2 may cause the V
10. Conditions: AV
11. The differential non-linearity (D
12. The ADC is monotonic; there are no missing codes.
13. The integral non-linearity (I
14. The offset error (OS
15. The gain error (G
16. The absolute voltage error (A
17. This should be considered when both analog and digital signals are simultaneously input to Port 1.
18. The parameter is guaranteed by design and characterized, but is not production tested.
2000 Jul 26
Single-chip 8-bit microcontroller with CAN controller
t
V
RST = Port 0 = V
be recognized as a logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.
HIGH to LOW. The transition current reaches its maximum value when V
Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these
pins make HIGH-to-LOW transitions during bus operations. In the worst cases (capacitive loading > 100pF), the
noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt
Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
no single outputs sinks more than 5 mA and no more than two outputs exceed in the test conditions.
specification when the address bits are stabilizing.
of 0.5 mV, derivating parameters from collected conversion results of ADC. AV
monotonic with not missing codes.
Fig.54).
transfer curve after appropriate adjustment of gain and offset error (see Fig.54).
removing gain error), and a straight line which fits the ideal transfer curve (see Fig.54).
removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point
on the transfer curve (see Fig.54).
of the non-calibrated ADC and the ideal transfer curve.
r
IL
= t
= V
f
= 10 ns; V
SS
+ 0.5 V; V
SS
IL
e
DD
= V
= 0 V; V
) is the relative difference in percent between the straight line fitting the actual transfer curve (after
; EA = XTAL1 = V
IH
e
SS
) is the absolute difference between the straight line which fits the actual transfer curve (after
= V
+ 0.5 V; V
DD
DD
Le
e
) is the peak difference between the centre of the steps of the actual and the ideal
= 5.0 V. Measurement by continuous conversion of AV
) is the maximum difference between the centre of the steps of the actual transfer curve
0.5 V; XTAL2 not connected; Port 0 = RST = V
Le
DD
) is the difference between the actual step width and the ideal step width (see
IH
test conditions.
= V
SS
DD
.
0.5 V; XTAL2 not connected; EA = Port 0 = V
OH
144
on ALE and PSEN to momentarily fall below the 0.9 V
2
C specification, so an input voltage below 1.5 V will
OL
IN
can exceed these conditions provided that
is approximately 2 V.
DD
REF+
; EA = V
(P8xC591) = 4.977 V, ADC is
IN
= 20 mV to 5.12 V in steps
SS
Preliminary Specification
.
DD
OL
; = RST = V
of ALE and
r
= t
P8xC591
f
= 10 ns;
SS
.
DD