P87C591VFA/00,512 NXP Semiconductors, P87C591VFA/00,512 Datasheet - Page 39

• Manufacturer Part Number: P87C591VFA/00,512
• Description: IC 80C51 MCU 16K OTP 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C591VFA/00,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: CAN, EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN, I2C, UART
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1256-5; 935268182512; P87C591VFAA

Philips Semiconductors
Notes to Table 16:
1. A Wake-Up Interrupt is also generated, if the CPU tries to set the Sleep bit while the CAN controller is involved in bus
2. In order to support high priority messages, the Receive Interrupt is forced immediately upon a received message,
12.5.6
The register allows to enable different types of interrupt sources which are signalled to the CPU. The Interrupt Enable
Register appears to the CPU as a read / write memory.
Table 17 Interrupt Enable Register (IER) CAN Addr. 4, bit interpretation
2000 Jul 26
IER.7
IER.6
IER.5
IER.4
IER.3
IER.2
IER.1
IER.0
BIT
Single-chip 8-bit microcontroller with CAN controller
activities or a CAN Interrupt is pending.
which has passed successfully an acceptance filter with high priority (see acceptance filter section). As long as only
messages are received via low priority acceptance filters, the receive interrupt is not forced until the FIFO is filled
with more bytes than programmed in the Rx Interrupt Level Register.
The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command “Release
Receive Buffer” will clear RI temporarily. If there is another message available within the FIFO after the release
command, RI is set again. Otherwise RI keeps cleared.
I
SYMBOL
NTERRUPT
WUIE
DOIE
BEIE
EPIE
ALIE
EIE
RIE
TIE
E
Bus Error
Interrupt Enable
Arbitration Lost
Interrupt Enable
Error Passive
Interrupt Enable
Wake-Up Interrupt
Enable
Data Overrun
Interrupt Enable
Error Interrupt
Enable
Transmit Interrupt
Enable
Receive Interrupt
Enable
NABLE
NAME
R
EGISTER
(IER)
1 (enabled) If a bus error has been detected, the CAN controller requests
0 (disabled)
1 (enabled) If the CAN controller has lost arbitration, the respective interrupt
0 (disabled)
1 (enabled) If the error status of the CAN controller changes from error
0 (disabled)
1 (enabled) If the sleeping CAN controller wakes up, the respective interrupt
0 (disabled)
1 (enabled) If the Data Overrun Status bit is set (see Status Register), the
0 (disabled)
1 (enabled) If the Error or Bus Status change (see Status Register), the
0 (disabled)
1 (enabled) When a message has been successfully transmitted or the
0 (disabled)
1 (enabled) When the Receive Buffer Status is ‘full’ the CAN controller
0 (disabled)
VALUE
the respective interrupt.
is requested.
active to error passive or vice versa, the respective interrupt is
requested.
is requested.
CAN controller requests the respective interrupt.
CAN controller requests the respective interrupt.
Transmit Buffer is accessible again, (e.g. after an Abort
Transmission command) the CAN controller requests the
respective interrupt.
requests the respective interrupt.
39
FUNCTION
Preliminary Specification
P8xC591