C8051F331-GM Silicon Laboratories Inc, C8051F331-GM Datasheet - Page 160
![IC 8051 MCU 8K FLASH 20QFN](/photos/12/16/121620/c8051f331-gm_sml.jpg)
C8051F331-GM
Manufacturer Part Number
C8051F331-GM
Description
IC 8051 MCU 8K FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F331-GM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F330DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
No. Of I/o's
17
Ram Memory Size
768Byte
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1451 - ADAPTER PROGRAM TOOLSTICK F330336-1264 - DEV KIT FOR C8051F330/F331
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1265
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F331-GM
Manufacturer:
SiliconL
Quantity:
1 630
Part Number:
C8051F331-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
C8051F331-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
C8051F330/1/2/3/4/5
17.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
17.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operat-
ing as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit
first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
17.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operat-
ing as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit
first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
17.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 gen-
erates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
17.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
See Figure 17.2, Figure 17.3, and Figure 17.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “
port I/O and crossbar information.
164
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as
NSS is disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode.
Since no select signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This
is intended for point-to-point communication between a master and one slave.
NSS is enabled as an input. When operating as a slave, NSS selects the SPI0 device. When
operating as a master, a 1-to-0 transition of the NSS signal disables the master function of
SPI0 so that multiple master devices can be used on the same SPI bus.
an output. The setting of NSSMD0 determines what logic level the NSS pin will output. This
configuration should only be used when operating SPI0 as a master device.
14. Port Input/Output
Rev. 1.7
” on page
123
for general purpose