C8051F331-GM Silicon Laboratories Inc, C8051F331-GM Datasheet - Page 174
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C8051F331-GM
Manufacturer Part Number
C8051F331-GM
Description
IC 8051 MCU 8K FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F331-GM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F330DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
No. Of I/o's
17
Ram Memory Size
768Byte
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1451 - ADAPTER PROGRAM TOOLSTICK F330336-1264 - DEV KIT FOR C8051F330/F331
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1265
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F331-GM
Manufacturer:
SiliconL
Quantity:
1 630
Part Number:
C8051F331-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
C8051F331-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
C8051F330/1/2/3/4/5
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to
“14.1. Priority Crossbar Decoder” on page 125
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 18.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 9.11). Setting GATE0 to ‘1’
allows the timer to be controlled by the external input signal /INT0 (see Section “
Descriptions
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 9.11).
18.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
178
Note: X = Don't Care
/IN T 0
T 0
TR0
0
1
1
1
C ro s s b a r
” on page
P re -s c a le d C lo c k
S Y S C L K
GATE0
IN 0 P L
X
0
1
1
89
G A T E 0
), facilitating pulse width measurements
X O R
Figure 18.1. T0 Mode 0 Block Diagram
T R 0
0
1
/INT0
M
H
T
3
X
X
0
1
M
T
3
L
C K C O N
M
H
T
2
T
M
2
L
0
1
M
T
1
M
T
0
C
S
A
1
S
C
A
0
Rev. 1.7
for information on selecting and configuring external I/O
Counter/Timer
G
A
T
E
1
C
T
1
/
Disabled
Disabled
Enabled
Enabled
M
T
1
1
T M O D
M
T
1
0
T C L K
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 b its )
T L 0
N
P
1
L
I
N
1
S
L
2
I
IT 0 1 C F
N
S
1
L
1
I
N
S
1
L
0
I
N
0
P
L
I
(8 b its )
T H 0
N
S
0
L
2
I
N
0
S
L
1
I
N
S
0
L
0
I
9.3.5. Interrupt Register
T R 1
T R 0
T F 1
T F 0
IE 1
IE 0
IT 1
IT 0
Section
In te rru p t