MC9S08JM60CGT Freescale Semiconductor, MC9S08JM60CGT Datasheet - Page 198
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MC9S08JM60CGT
Manufacturer Part Number
MC9S08JM60CGT
Description
IC MCU 8BIT 60K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08JM32CLD.pdf
(388 pages)
Specifications of MC9S08JM60CGT
Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
37
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 12-bit
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
24MHz
Total Internal Ram Size
4KB
# I/os (max)
37
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
QFN EP
Package
48QFN EP
Family Name
HCS08
Maximum Speed
24 MHz
Operating Supply Voltage
3.3|5 V
For Use With
DEMOJM - KIT DEMO FOR JM MCU FAMILYDEMOJMSKT - BOARD DEMO S08JM CARD W/SOCKET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Multi-Purpose Clock Generator (S08MCGV1)
BDIV=01 (divide by 2), RDIV < 011
12.5
This section describes how to initialize and configure the MCG module in application. The following
sections include examples on how to initialize the MCG and properly switch between the various available
modes.
12.5.1
The MCG comes out of reset configured for FEI mode with the BDIV set for divide-by-2. The internal
reference will stabilize in t
reference is stable, the FLL will acquire lock in t
Upon POR, the internal reference will require trimming to guarantee an accurate clock. Freescale
recommends using FLASH location 0xFFAE for storing the fine trim bit, FTRIM in the MCGSC register,
and 0xFFAF for storing the 8-bit trim value in the MCGTRM register. The MCU will not automatically
copy the values in these FLASH locations to the respective registers. Therefore, user code must copy these
values from FLASH to the registers.
12.5.1.1
Because the MCG comes out of reset in FEI mode, the only MCG modes which can be directly switched
to upon reset are FEE, FBE, and FBI modes (see
first configuring the MCG for one of these three initial modes. Care must be taken to check relevant status
bits in the MCGSC register reflecting all configuration changes within each mode.
To change from FEI mode to FEE or FBE modes, follow this procedure:
198
1. Enable the external clock source by setting the appropriate bits in MCGC2.
2. Write to MCGC1 to select the clock mode.
— If entering FEE, set RDIV appropriately, clear the IREFS bit to switch to the external reference,
— If entering FBE, clear the IREFS bit to switch to the external reference and change the CLKS
— The internal reference can optionally be kept running by setting the IRCLKEN bit. This is
Initialization / Application Information
and leave the CLKS bits at %00 so that the output of the FLL is selected as the system clock
source.
bits to %10 so that the external reference clock is selected as the system clock source. The
RDIV bits should also be set appropriately here according to the external reference frequency
because although the FLL is bypassed, it is still on in FBE mode.
useful if the application will switch back and forth between internal and external modes. For
MCG Module Initialization Sequence
Initializing the MCG
•
The BDIV value should not be changed to divide-by-1 without first
trimming the internal reference. Failure to do so could result in the MCU
running out of specification.
BDIV=00 (divide by 1), RDIV < 010
irefst
microseconds before the FLL can acquire lock. As soon as the internal
MC9S08JM60 Series Data Sheet, Rev. 3
fll_lock
NOTE
Figure
milliseconds.
12-8). Reaching any of the other modes requires
Freescale Semiconductor
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