MC9S08JM60CGT Freescale Semiconductor, MC9S08JM60CGT Datasheet - Page 319
![IC MCU 8BIT 60K FLASH 48-QFN](/photos/12/17/121757/mc9s08jm60cgt_sml.jpg)
MC9S08JM60CGT
Manufacturer Part Number
MC9S08JM60CGT
Description
IC MCU 8BIT 60K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08JM32CLD.pdf
(388 pages)
Specifications of MC9S08JM60CGT
Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
37
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 12-bit
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
24MHz
Total Internal Ram Size
4KB
# I/os (max)
37
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
QFN EP
Package
48QFN EP
Family Name
HCS08
Maximum Speed
24 MHz
Operating Supply Voltage
3.3|5 V
For Use With
DEMOJM - KIT DEMO FOR JM MCU FAMILYDEMOJMSKT - BOARD DEMO S08JM CARD W/SOCKET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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17.4.3
When the USB module transmits or receives data, it will first compute the BDT address based on the
endpoint number, data direction, and which buffer is being used (even or odd), then it will read the BD.
Once the BD has been read, and if the OWN bit equals 1, the serial interface engine (SIE) will transfer the
packet data to or receive the packet data from the buffer pointed to by the EPADR field of the BD. When
the USB TOKEN is complete, the USB module will update the BDT and change the OWN bit to 0.
The STAT register is updated and the TOKDNE interrupt is set. When the microcontroller processes the
TOKDNE interrupt, it reads the status register. This gives the microcontroller all the information it needs
to process the endpoint. At this point the microcontroller can allocate a new BD, so additional USB data
can be transmitted or received for that endpoint, and it can process the previous BD.
a timeline for how a typical USB token would be processed.
Freescale Semiconductor
EPADR[9:4]
BC[7:0]
Field
USB Transactions
Byte Count — The Byte Count bits represent the 8-bit byte count. The USB module serial interface engine
(SIE) will change this field upon the completion of a RX transfer with the byte count of the data received. Note
that while USB supports packets as large as 1023 bytes for isochronous endpoints, this module limits packet
size to 64 bytes.
Endpoint Address— The endpoint address bits represent the upper 6 bits of the 10-bit buffer address within
the module’s local USB RAM. Bits [3:0] of EPADR are always zero, therefore the address of the buffer must
always start on a 16-byte aligned address within the local RAM. These bits are unchanged by the USB module.
This is NOT the address of the memory on the system bus. EPADR is relative to the start of the local USB RAM.
Table 17-22. Buffer Descriptor Table Fields (continued)
MC9S08JM60 Series Data Sheet, Rev. 3
Description
Universal Serial Bus Device Controller (S08USBV1)
Figure 17-20
shows
319
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