MC9S08DZ60ACLF Freescale Semiconductor, MC9S08DZ60ACLF Datasheet - Page 139

• Manufacturer Part Number: MC9S08DZ60ACLF
• Description: IC MCU 60K FLASH 4K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ60ACLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DZ
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• For Use With: DEMO9S08DZ60 - BOARD DEMOEVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.5.11
Port L is controlled by the registers listed below.
6.5.11.1
6.5.11.2
Freescale Semiconductor
PTLDD[7:0]
PTLD[7:0]
Reset:
Reset:
Field
Field
7:0
7:0
W
W
R
R
PTLDD7
PTLD7
Port L Registers
Port L Data Register Bits — For port L pins that are inputs, reads return the logic level on the pin. For port L
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port L pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTLD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
Data Direction for Port L Bits — These read/write bits control the direction of port L pins and what is read for
PTLD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port L bit n and PTLD reads return the contents of PTLDn.
Port L Data Register (PTLD)
0
Port L Data Direction Register (PTLDD)
0
7
7
PTLDD6
PTLD6
0
0
6
6
Figure 6-66. Port L Data Direction Register (PTLDD)
Table 6-64. PTLDD Register Field Descriptions
Table 6-63. PTLD Register Field Descriptions
Figure 6-65. Port L Data Register (PTLD)
MC9S08DZ128 Series Data Sheet, Rev. 1
PTLDD5
PTLD5
0
0
5
5
PTLDD4
PTLD4
0
0
4
4
Description
Description
PTLDD3
PTLD3
3
0
3
0
PTLDD2
PTLD2
Chapter 6 Parallel Input/Output Control
0
0
2
2
PTLDD1
PTLD1
0
0
1
1
PTLDD0
PTLD0
0
0
0
0
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