MC9S08DZ60ACLF Freescale Semiconductor, MC9S08DZ60ACLF Datasheet - Page 439

• Manufacturer Part Number: MC9S08DZ60ACLF
• Description: IC MCU 60K FLASH 4K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ60ACLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DZ
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• For Use With: DEMO9S08DZ60 - BOARD DEMOEVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
3
4
When any reset is initiated, internal circuitry drives the RESET pin low for about 34 cycles of f
clock frequency changes to the untrimmed DCO frequency (f
to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets, trim stays at the pre-reset value.
Timing is shown with respect to 20% V
RESET PIN
Q/PIAx/PIBx/PIDx/PIJx
Figure A-11. Active Background Debug Mode Latch Timing
PIAx/PIBx/PIDx/PIJx
BKGD/MS
RESET
DD
MC9S08DZ128 Series Data Sheet, Rev. 1
Figure A-12. Pin Interrupt Timing
and 80% V
Figure A-10. Reset Timing
t
MSSU
DD
levels. Temperature range –40°C to 125°C.
reset
t
t
= (f
IHIL
ILIH
t
extrst
dco_ut
)/4) because TRIM is reset to 0x80, FTRIM is reset
t
MSH
Appendix A Electrical Characteristics
sys
. After POR reset, the bus
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