MC908GR16ACFAE Freescale Semiconductor, MC908GR16ACFAE Datasheet - Page 121

• Manufacturer Part Number: MC908GR16ACFAE
• Description: IC MCU 16K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR16ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1
to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.
DDRB7–DDRB0 — Data Direction Register B Bits
Figure 12-8
When bit DDRBx is a 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a 0,
reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Freescale Semiconductor
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
These read/write bits control port B data direction. Reset clears DDRB7–DDRB0, configuring all port
B pins as inputs.
DDRB
Bit
0
1
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
shows the port B I/O logic.
PTB
Address:
X
Bit
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
X
(1)
Reset:
Read:
Write:
READ DDRB ($0005)
WRITE DDRB ($0005)
WRITE PTB ($0001)
READ PTB ($0001)
DDRB7
$0005
Bit 7
Input, Hi-Z
0
I/O Pin
Output
Figure 12-7. Data Direction Register B (DDRB)
Mode
DDRB6
(2)
6
0
MC68HC908GR16A Data Sheet, Rev. 1.0
Table 12-3. Port B Pin Functions
RESET
Figure 12-8. Port B I/O Circuit
DDRB5
5
0
Accesses to DDRB
DDRB7–DDRB0
DDRB7–DDRB0
Table 12-3
Read/Write
NOTE
DDRB4
DDRBx
PTBx
4
0
summarizes the operation of the port B pins.
DDRB3
3
0
DDRB2
PTB7–PTB0
2
0
Read
Pin
DDRB1
Accesses to PTB
1
0
DDRB0
Bit 0
PTBx
0
PTB7–PTB0
PTB7–PTB0
Write
(3)
Port B
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